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IEEE
Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems |
| 2009 Issues |
| Editorial 2009 |
Keynote Paper
- R. Marculescu, U. Y. Ogras, L.-S. Peh, N. E. Jerger and Y. Hoskote, Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (4729)
Regular Issue
- Irith Pomeranz and Sudhakar M. Reddy, Functional Broadside Tests under an Expanded Definition of Functional Operation Conditions (4635)
- Smita Krishnaswamy, Stephen M. Plaza, Igor L. Markov and John P. Hayes, Signature-based SER Analysis and Design of Logic Circuits (4626)
- Jia-Wei Fang, Chin-Hsiung Hsu and Yao-Wen Chang, An Integer Linear Programming Based Routing Algorithm for Flip-Chip Designs (4616)
- Jung Hwan Choi, Nilanjan Banerjee and Kaushik Roy, Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters (4613)
- Paolo Maffezzoni and Dario D'Amore, Evaluating Pulling Effects in Oscillators due to Small-Signal Injection (4695)
- Lerong Cheng, Jinjun Xiong and Lei He, Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting (4581)
- Ender Yilmaz and Gunhan Dundar, Analog Layout Generator for CMOS Circuits (4676)
- Jing Li, Kunhyuk Kang and Kaushik Roy, Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low Power, Low-Cost Applications (4520)
- Sudarshan Bahukudumbi and Krishnendu Chakrabarty, Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs (4659)
- Zhuo Feng, Peng Li and Yaping Zhan, An On-the-Fly Parameter Dimension Reduction Approach to Fast Second-Order (4348)
- María C. Molina, Rafael Ruiz-Sautua, Pedro L. García and Román Hermida, Frequent-pattern Guided Multi-level Decomposition of Behavioural Specifications (4641)
Short Papers:
- Gianpiero Cabodi, Sergio Nocco and Stefano Quer, Strengthening Model Checking Techniques with Inductive Invariants (4646)
- Hoseok Chang and Wonyong Sung, Access Pattern Aware On-Chip Memory Allocation for SIMD Processors (4645)
- Zhanglei Wang, Hongxia Fang, Krishnendu Chakrabarty and Michael Bienek, Deviation-Based LFSR Reseeding for Test-Data Compression (4702)
- Huaizhi Wu and Martin D.F. Wong, Incremental Improvement of Voltage assignment (4663)
- Cheng-Hong Li and Luca P. Carloni, Leveraging Local Intra-Core Information to Increase Global Performance in Block-Based Design of Systems-on-Chip (4649)
- Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta and Xian-Long Hong, Substrate Topological Routing for High Density Packages (4618)
- V. J. Mehta, M. Marek-Sadowska, K.-H. Tsai and J. Rajski, Timing-Aware Multiple-Delay-Fault Diagnosis (4591)
- Tai-Ying Jiang, Chien-Nan Jimmy Liu and Jing-Yang Jou, Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging (4777)
- Ho Fai Ko and Nicola Nicolici, Algorithms for State Restoration and Trace Signals Selection for Data Acquisition in Silicon Debug (4583)
- Kristofer Vorwerk, Andrew Kennings and Jonathan Greene, Improving Simulated Annealing-Based FPGA Placement with Directed Moves (4760)
- Cristian Soviani, Ilija Hadzic and Stephen A. Edwards, Synthesis and Optimization of Pipielined Packet Processors (4747)
- Huang-Yu Chen, Szu-Jui Chou, Sheng-Lung Wang and Yao-Wen Chang, A Novel Wire Density Driven Full-Chip Routing System for CMP Variation Control (4723)
Short Papers:
- Sobeeh Almukhaizim and Ozgur Sinanoglu, Dynamic Scan Chain Partitioning For Reducing Peak Shift Power During Test (4691)
- Alessandro Pinto, Luca P. Carloni and Alberto L. Sangiovanni Vincentelli, A Methodology for Constrained-Driven Synthesis of On-Chip Communications (4469)
- Irith Pomeranz and Sudhakar M. Reddy, Double-Single Stuck-At Faults: A Delay Fault Model for Synchronous Sequential Circuits (4765)
- Dipanjan Sengupta and Resve Saleh, Application-Driven Voltage Island Partitioning for Low-power System-on-Chip Design (4748)
- Qiang Liu, George A. Constantinides, Konstantinos Masselos and Peter Y. K. Cheung, Combining Data Reuse with Data-Level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework (4744)
- Yu-Min Kuo, Yue-Lung Chang and Shih-Chieh Chang, Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation (4739)
- , Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements (4853)
- Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy and Peter Harrod, Diagnosis of Multiple-Voltage Design with Bridge Defect (4838)
- Muhammet Mustafa Ozdal, Detailed Routing Algorithms for Dense Pin Clusters in Integrated Circuits (4816)
- Hushrav D Mogal, Haifeng Qian, Sachin S Sapatnekar and Kia Bazargan, Fast and Accurate Statistical Criticality Computation under Process Variations (4625)
- M. Ruggiero, A. Guerri, D. Bertozzi, L. Benini, M. Milano and A. Andrei, Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms (4806)
- M. R. Choudhury and K. Mohanram, Reliability Analysis of Logic Circuits (4660)
- H. Yao and H. Zheng, Automated Interface Refinement for Compositional Verification (4783)
Short Papers:
- Angelo Brambilla, Giambattista Gruosso and Giancarlo Storti Gajani, Determination of Floquet Exponents for Small Signal Analysis of Nonlinear Periodic Circuits (4792)
- Aviral Shrivastava, Ilya Issenin, Nikil Dutt, Sanghyun Park and Yunheung Paek, Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures (4790)
- Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang and Malgorzata Marek-Sadowska, Spare Cells with Constant Insertion for Engineering Change (4727)
- Eunjoo Choi, Changsik Shin and Youngsoo Shin, HLS-pg: High-Level Synthesis of Power-Gated Circuits (4627)
- Haralampos-G. Stratigopoulos, Salvador Mir and Achène Bounceur, Evaluation of Analog/RF Test Measurements at the Design Stage (4895)
- Vittorio Rizzoli, Franco Mastri, Alessandra Costanzo and Diego Masotti, Harmonic Balance Algorithms for the Circuit-Level Nonlinear Analysis of UWB Receivers (4860)
- Yongfeng Feng and A. H. Mantooth, Algorithms for Automatic Model Topology Formulation (4742)
- Jungsoo Kim, Seungyong Oh, Sungjoo Yoo and Chong-Min Kyung, An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-aware Workload and Runtime Distribution (4857)
- Muhammet Mustafa Ozdal and Martin D. F. Wong, Archer: A History Based Global Routing Algorithm (4428)
- Behnam Amelifard, Farzan Fallah and Massoud Pedram, Low-Power Fanout Optimization using Multi Threshold Voltages and Multi Channel Lengths (4842)
- Pramod Kumar Meher, Extended Sequential Logic for Synchronous Circuit Optimization and its Applications (4832)
- Wei Dong and Peng Li, A Parallel Harmonic Balance Approach to Steady-state and Envelope-following Simulation of Driven and Autonomous Circuits (4823)
- Takashi Enami, Shinyu Ninomiya and Masanori Hashimoto, Statistical Timing Analysis Considering Spatially and Temporally Correlated (4799)
- Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil Dutt and Yunheung Paek, Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications (4786)
Short Papers:
- Yu Hu, Satyaki Das, Steve Trimberger and Lei he, Design and Synthesis of Programmable Logic Block with Mixed LUT and Macro-Gate (4751)
- Shuo Wang and Lei Wang, Analysis of Deskew Signaling via Adaptive Timing (4821)
- Alodeep Sanyal, Kunal Ganeshpure and Sandip Kundu, An Improved Soft Error Rate Measurement Technique (4789)
WINNER of the 2009 DONALD O. PEDERSON BEST PAPER AWARD
- H. Nikolov, T. Stefanov and E. Deprettere, Systematic and Automated Multiprocessor System Design, Programming, and Implementation (3842)
Regular Issue
- I. Vytyaz, C. D. Lee, P. K. Hanumolu, U.-K. Moon and K. Mayaram, Automated Design and Optimization of Low-Noise Oscillators (4900)
- Y. Xu, K.-L. Hsiung, L. T. Pileggi and S. P. Boyd, Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty (4901)
- Y. J. Chong and S. Parameswaran, Custom Floating-Point Unit Generation for Embedded Systems (4854)
- P. Banerjee, S. Sur-Kolay and A. Bishnu, Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs (4698)
- R. Cordone, F. Redaelli, M. A. Redaelli, M. D. Santambrogio and D. Sciuto, Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs (4923)
- G. Dhiman and T. S. Rosing, System-Level Power Management Using Online Learning (4858)
- W.-P. Lee, H.-Y. Liu and Y.-W. Chang, Voltage-Island Partitioning and Floorplanning Under Timing Constraints (4931)
- D. Grosse, R. Wille, G. W. Dueck and R. Drechsler, Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques (4824)
- S.-J. Wang, K. S.-M. Li, S.-C. Chen, H.-Y. Shiu and Y.-L. Chu, Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint (4930)
- A. DeOrio, A. B. Bauserman, V. Bertacco and B. C. Isaksen, Inferno: Streamlining Verification With Inferred Semantics (4808)
- O. Sarbishei, M. Tabandeh, B. Alizadeh and M. Fujita, A Formal Approach for Debugging Arithmetic Circuits (4714)
Short Papers:
- A. S. Abu-Issa and S. F. Quigley, Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST (4872)
- K. Fujiyoshi, H. Kawai and K. Ishihara, A Tree Based Novel Representation for 3D-Block Packing (4834)
- C.-W. Tzeng, H.-C. Cheng and S.-Y. Huang, Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects (4664)
- Y. Wang, S. Joeres, R. Wunderlich and S. Heinen, Modeling Approaches for Functional Verification of RF-SoCs: Limits and Future Requirements (4967)
Keynote Paper
- De Micheli, G., An Outlook on Design Technologies for Future Integrated Systems
Regular Issue
- Lin, P.-H.; Chang, Y.-W.; Lin, S.-C., Analog Placement Based on Symmetry-Island Formulation
- Agosta, G.; Bruschi, F.; Pelosi, G.; Sciuto, D., A Transform-Parametric Approach to Boolean Matching
- Hu, S.; Ketkar, M.; Hu, J., Gate Sizing for Cell-Library-Based Designs
- Dai, H.; Knepper, R. W., Modeling and Experimental Measurement of Active Substrate-Noise Suppression in Mixed-Signal 0.18-um BiCMOS Technology
- Das, S.; Sural, S.; Patra, A., Resistance Estimation for Lateral Power Arrays Through Accurate Netlist Generation
- Han, K. J.; Swaminathan, M., Inductance and Resistance Calculations in Three-Dimensional Packaging Using Cylindrical Conduction-Mode Basis Functions
- Hassan, Z.; Allec, N.; Shang, L.; Dick, R. P.; Venkatraman, V.; Yang, R., Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits
- Heloue, K. R.; Azizi, N.; Najm, F. N., Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation
- Amelifard, B.; Pedram, M., Optimal Design of the Power-Delivery Network for Multiple Voltage-Island SoCs
- Ozturk, O.; Kandemir, M.; Irwin, M. J., Using Data Compression for Increasing Memory System Utilization
- Favalli, M.; Metra, C., Testing Resistive Opens and Bridging Faults Through Pulse Propagation
Short Papers:
- Jun, M.; Yoo, S.; Chung, E.-Y., Topology Synthesis of Cascaded Crossbar Switches
Special Section
- Sangiovanni-Vicentelli, A.; Di Natale, M., Challenges and Solutions in the Development of Automotive Systems
- Ergen, S. C.; Sangiovanni-Vincentelli, A.; Sun, X.; Tebano, R.; Alalusi, S.; Audisio, G.; Sabatini, M., The Tire as an Intelligent Sensor
- Obermaisser, R.; El Salloum, C.; Huber, B.; Kopetz, H., From a Federated to an Integrated Automotive Architecture
- Wilhelm, R.; Grund, D.; Reineke, J.; Schlickling, M.; Pister, M.; Ferdinand, C., Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
- Schliecker, S.; Rox, J.; Negrean, M.; Richter, K.; Jersak, M.; Ernst, R., System Level Performance Analysis for Real-Time Automotive Multicore and Network Architectures
Regular Issue
- Acar, E.; Ozev, S., Low-Cost Characterization and Calibration of RF Integrated Circuits through IQ Data Analysis
- Cho, M.; Yuan, K.; Ban, Y.; Pan, D. Z., ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction
- Chouhan, S.; Bose, R.; Balakrishnan, M., A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes
- Dal, D.; Mansouri, N., Power Optimization With Power Islands Synthesis
- Mukhopadhyay, S., A Generic Data-Driven Nonparametric Framework for Variability Analysis of Integrated Circuits in Nanometer Technologies
- Srivastava, N.; Suaya, R.; Banerjee, K., Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate
- Thakker, R. A.; Sathe, C.; Sachid, A. B.; Shojaei Baghini, M.; Ramgopal Rao, V.; Patil, M. B., A Novel Table-Based Approach for Design of FinFET Circuits
- Wang, J.; Das, D.; Zhou, H., Gate Sizing by Lagrangian Relaxation Revisited
- Lin, C.-H.; Wang, C.-Y.; Chen, Y.-C., Dependent-Latch Identification in Reachable State Space
- Banerjee, N.; Karakonstantis, G.; Choi, J. H.; Chakrabarti, C.; Roy, K., Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering
- Chen, D.; Jiao, D., Time-Domain Orthogonal Finite-Element Reduction-Recovery Method for Electromagnetics-Based Analysis of Large-Scale Integrated Circuit and Package Problems
- Elfadel, I. M., Convergence of Transverse Waveform Relaxation for the Electrical Analysis of Very Wide Transmission Line Buses
- McConaghy, T.; Gielen, G. G. E., Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming
- Singhee, A.; Rutenbar, R. A., Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design
- Zeng, Z.; Li, P., Locality-Driven Parallel Power Grid Optimization
- Liu, Q.; Sapatnekar, S. S., A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations
- Chiou, L.-Y.; Chen, Y.-S.; Lee, C.-H., System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm
- Qin, X.; Mishra, P., A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression
- Weerasekera, R.; Pamunuwa, D.; Zheng, L.-R.; Tenhunen, H., Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints
- Wang, Z.; Chakrabarty, K.; Wang, S., Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip
Short Papers:
- Huang, S.-H.; Cheng, C.-H., Minimum-Period Register Binding
- Ingelsson, U.; Al-Hashimi, B. M.; Khursheed, S.; Reddy, S. M.; Harrod, P., Process Variation-Aware Test for Resistive Bridges
- Kim, M.-J.; Chung, E.-Y.; Yoon, S., High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation
- McConaghy, T.; Palmers, P.; Steyaert, M.; Gielen, G. G. E., Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy
- Yuh, P.-H.; Sapatnekar, S. S.; Yang, C.-L.; Chang, Y.-W., A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips
- Zhang, J.; Patil, N. P.; Mitra, S., Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits
- Ciesielski, M.; Gomez-Prado, D.; Ren, Q.; Guillot, J.; Boutillon, E., Optimization of Data-Flow Computations Using Canonical TED Representation
- Bang, S.-Y.; Bang, K.; Yoon, S.; Chung, E.-Y., Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling
- Zhang, W.; Yu, W.; Hu, X.; Zhang, L.; Shi, R.; Peng, H.; Zhu, Z.; Chua-Eoan, L.; Murgai, R.; Shibuya, T., Efficient Power Network Analysis Considering Multidomain Clock Gating
- Gad, E.; Nakhla, M.; Achar, R.; Zhou, Y., A-Stable and L-Stable High-Order Integration Methods for Solving Stiff Differential Equations
- Pathak, M.; Lim, S. K., Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs
- Daoud, E. A.; Nicolici, N., Real-Time Lossless Compression for Silicon Debug
- Chun, S.; Kim, T.; Kang, S., ATPG-XP: Test Generation for Maximal Crosstalk-Induced Faults
- Xiong, J.; Zolotov, V.; Visweswariah, C.; Habitz, P. A., Optimal Test Margin Computation for At-Speed Structural Test
Short Papers:
- Stevanovic, I.; McAndrew, C. C., Quadratic Backward Propagation of Variance for Nonlinear Statistical Circuit Modeling
- Pomeranz, I.; Reddy, S. M., Forward-Looking Reverse Order Fault Simulation for n-Detection Test Sets
Keynote Paper
- Carmona, J.; Cortadella, J.; Kishinevsky, M.; Taubin, A., Elastic Circuits
Regular Issue
- Harutyunyan, D.; Rommes, J.; ter Maten, J.; Schilders, W., Simulation of Mutually Coupled Oscillators Using Nonlinear Phase Macromodels
- Bond, B. N.; Daniel, L., Stable Reduced Models for Nonlinear Descriptor Systems Through Piecewise-Linear Approximation and Projection
- Roy, S.; Dounavis, A., Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects Using a Matrix Rational Approximation
- Chakraborty, R. S.; Bhunia, S., HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection
- Coskun, A. K.; Rosing, T. S.; Gross, K. C., Utilizing Predictors for Efficient Thermal Management in Multiprocessor SoCs
- Gerstlauer, A.; Haubelt, C.; Pimentel, A. D.; Stefanov, T. P.; Gajski, D. D.; Teich, J., Electronic System-Level Synthesis Methodologies
- Lee, W. Y.; Kim, H.; Lee, H., Maximum-Utility Scheduling of Operation Modes With Probabilistic Task Execution Times Under Energy Constraints
- Park, S.-B.; Hong, T.; Mitra, S., Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)
- Rao, R.; Vrudhula, S., Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints
- Ahmed, N.; Tehranipoor, M., A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects
- Wang, S.-J.; Yeh, T.-H., High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability
- Safarpour, S.; Veneris, A., Automated Design Debugging With Abstraction and Refinement
- Bronckers, S.; Scheir, K.; Van der Plas, G.; Vandersteen, G.; Rolain, Y., A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems
- McConaghy, T.; Gielen, G. G. E., Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy
- Ye, Z.; Zhu, Z.; Phillips, J. R., Incremental Large-Scale Electrostatic Analysis
- Chen, Q.; Choi, H. W.; Wong, N., Robust Simulation Methodology for Surface-Roughness Loss in Interconnect and Package Modelings
- Wu, T.-H.; Davoodi, A., PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design
- Yan, T.; Wong, M. D. F., BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology
- Alimonda, A.; Carta, S.; Acquaviva, A.; Pisano, A.; Benini, L., A Feedback-Based Approach to DVFS in Data-Flow Applications
- Chu, E. T.-H.; Huang, T.-Y.; Tsai, Y.-C., An Optimal Solution for the Heterogeneous Multiprocessor Single-Level Voltage-Setup Problem
- Shrivastava, A.; Kannan, A.; Lee, J., A Software-Only Solution to Use Scratch Pads for Stack Data
- Callegari, N.; Bastani, P.; Wang, L.-C.; Abadir, M. S., A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch
- Czysz, D.; Kassab, M.; Lin, X.; Mrugalski, G.; Rajski, J.; Tyszer, J., Low-Power Scan Operation in Test Compression Environment
- Tzeng, C.-W.; Huang, S.-Y., QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test
- Wu, M.-F.; Huang, J.-L.; Wen, X.; Miyase, K., Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment
Short Papers
- Cheng, L.; Gupta, P.; He, L., Efficient Additive Statistical Leakage Estimation
Special Section on the IEEE Symposium on Application Specific Processors 2008
- Orailoglu, A.; Pozzi, L., Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008
- Zuluaga, M.; Topham, N., Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions
- Spjut, J.; Kensler, A.; Kopta, D.; Brunvand, E., TRaX: A Multicore Hardware Architecture for Real-Time Ray Tracing
- Palermo, G.; Silvano, C.; Zaccaria, V., ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration
- Han, W.; Yi, Y.; Muir, M.; Nousias, I.; Arslan, T.; Erdogan, A. T., Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies
Regular Issue
- Chen, J.; Chang, C.-H., High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier
- Beltrame, G.; Fossati, L.; Sciuto, D., ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration
- Mulas, F.; Atienza, D.; Acquaviva, A.; Carta, S.; Benini, L.; De Micheli, G., Thermal Balancing Policy for Multiprocessor Stream Computing Platforms
- Jiang, Z.; Gupta, S. K., Threshold Testing: Improving Yield for Nanoscale VLSI
- Stevanovic, I.; McAndrew, C. C., Corrections to "Quadratic Backward Propagation of Variance for Nonlinear Statistical Circuit Modeling" [Sep 09 1428-1432]
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