January 2008

• Andrew B. Kahng and Kambiz Samadi, SURVEY: CMP Fill Synthesis: A Survey of Recent Studies (3653)

• V. Vankamamidi, M. Ottavi and F. Lombardi, Two-Dimensional Schemes for Clocking/Timing of QCA Circuits (3628)

• Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee and Mark Kassab, X-Press: Two-Stage X-Tolerant Compactor with Programmable Selector (3762)

• Irith Pomeranz and Sudhakar M. Reddy, Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation (3503)

• Muhammet Mustafa Ozdal, Martin D. F. Wong and Philip S. Honsinger, Simultaneous Escape Routing Algorithms For Via Minimization of High-Speed Boards (3757)

• Saibal Mukhopadhyay, Hamid Mahmoodi and Kaushik Roy, Reduction of Parametric Failures in Sub-100nm SRAM Array using Body Bias (3462)

• Ting Mei and Jaijeet Roychowdhury, A Time-Domain Oscillator Envelope Tracking Algorithm employing Dual Phase Conditions (3707)

• Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini and Jan Madsen, A Reactive and Cycle-True IP Emulator for MPSoC Exploration (3361)

• D. Arumí, R. Rodríguez-Montañés and J. Figueras, Experimental Characterization of CMOS Interconnect Open Defects (3685)

• Chris Chu and Yiu-Chung Wong, FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design (3673)

• Shrirang K. Karandikar and Sachin S. Sapatnekar, Technology Mapping Using Logical Effort Solving the Load Distribution Problem (3670)

• Amit Kumar, Li Shang, Li-Shiuan Peh and Niraj K. Jha, System-Level Dynamic Thermal Management for High Performance Microprocessors (3657)

• Jaskirat Singh and Sachin Sapatnekar, A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations (3792)

Short Papers:

• Sushanta K. Mandal, Shamik Sural and Amit Patra, ANN and PSO based Synthesis of On-Chip Spiral Inductors for RF ICs (3778)

• Kai-hui Chang, Igor L. Markov and Valeria Bertacco, Fixing Design Errors with Counterexamples and Resynthesis (3686)

• Irith Pomeranz and Sudhakar M. Reddy, Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits (3868)

• Weixin Wu and Michael S. Hsiao, Mining Global Constraints with Domain Knowledge for Improving Bounded Sequential Equivalence Checking (3803)

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February 2008

• Tung-Chieh Chen, Yao-Wen Chang and Shyh-Chang Lin, A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning (3665)

• Javid Jaffari and Mohab Anis, Variability-Aware Bulk-MOS Device Design (3845)

• R. Mahesh and A. P. Vinod, A New Common Subexpression Elimination Algorithm for Realizing Low Complexity Higher Order Digital Filters (3658)

• A. Heldring, J.M. Rius, J.M. Tamayo and J. Parrón, Compressed Block Decomposition Algorithm for Fast Capacitance Extraction (3840)

• Ja Chun Ku and Yehea Ismail, Area Optimization for Leakage Reduction and Thermal Stability in Nanometer Scale Technologies (3420)

• , A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance (3900)

• Shantanu Dutt, Vinay Verma and Vishal Suthar, Built-in-Self-Test of FPGAs with Provable Diagnosabilities and High Diagnostic Coverage with Application to On-Line Testing (3385)

• Ilya Wagner, Valeria Bertacco and Todd Austin, Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors (3821)

• A.B. Kahng, S. Muddu and P. Sharma, Defocus-Aware Leakage Estimation and Control (3890)

• Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri and Bernd Becker, On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing (3820)

• Zhanglei Wang and Krishnendu Chakrabarty, Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns (3887)

• Jaskirat Singh, Zhi-Quan Luo and Sachin Sapatnekar, A Geometric Programming-based Worst-Case Gate Sizing Method Incorporating Spatial Correlation (3818)

• Ning Dong and Jaijeet Roychowdhury, General-Purpose Nonlinear Model Order Reduction Using Piecewise Polynomial Representations (3738)

• Himanshu Jain, Daniel Kroening, Natasha Sharygina and Edmund Clarke, Word Level Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog (3727)

• Haralampos-G. Stratigopoulos and Yiorgos Makris, Error Moderation in Low-Cost Machine Learning-Based Analog/RF Testing (3847)

Short Papers:

• Aleksandra Sesic, Stanisa Dautovic and Veljko Malbasa, Dynamic Power Management of a System with a Two-Priority Request Queue Using Probabilistic Model Checking (3826)

• Hiren D Patel and Sandeep K. Shukla, On Co-simulating Multiple Abstraction Level System Level Models (3859)

• Irith Pomeranz and Sudhakar M. Reddy, Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test (3856)

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March 2008

• Baolin Yang, Yu Zhu, Ali Bouaricha and Joel Phillips, Applications of the Multi-interval Chebyshev Collocation Method in RF Circuit Simulation (3656)

• Peter Hallschmid and Resve Saleh, Fast Design Space Exploration using Local Regression Modeling with Applications to ASIPs (3918)

• Sarvesh Bhardwaj and Sarma Vrudhula, Leakage Minimization of Digital Circuits using Gate Sizing in the presence of Process Variations (3228)

• Sejong Oh, Tag Gon Kim, Jung Hoon Cho and Elaheh Bozorgzadeh, Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration (3880)

• Kubilay Atasu, Can Ozturan, Gunhan Dundar, Oskar Mencer and Wayne Luk, CHIPS: Custom Hardware Instruction Processor Synthesis (4010)

• Kin Cheong Sou, Alexandre Megretski and Luca Daniel, A Quasi-Convex Optimization Approach to Parameterized Model Order Reduction (3873)

• Sarvesh H. Kulkarni, Dennis Sylvester and David Blaauw, Design-Time Optimization of Post-Silicon Tuned Circuits using Adaptive Body Bias (3995)

• Ngai Wong, Efficient Positive-Real Balanced Truncation of Symmetric Systems Via Cross Riccati Equations (3844)

• Seda Ogrenci Memik, Rajarshi Mukherjee, Min Ni and Jieyi Long, Optimizing Thermal Sensor Allocation for Microprocessors (3986)

• Hristo Nikolov, Todor Stefanov and Ed Deprettere, Systematic and Automated Multi-processor System Design, Programming and Implementation (3842)

• D. Maslov, G. W. Dueck, D. M. Miller and C. Negrevergne, Quantum Circuit Simplification and Level Compaction (3972)

• Andrew C. Ling, Jianwen Zhu and Stephen D. Brown, Scalable Technology Mapping and Clustering Techniques using Decision Diagrams (3825)

• Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal and Pramod Kumar, An Equivalence Checking Method for Scheduling Verification in High-level Synthesis (3945)

Short Papers:

• P. Bernardi, E. Sánchez, M. Schillaci, G. Squillero and M. Sonza Reorda, An Effective technique for the Automatic Generation of Diagnosis-oriented Programs for Processor Cores (3917)

• Hangkyu Lee, Irith Pomeranz and Sudhakar M. Reddy, On Complete Functional Broadside Tests for Transition Faults (3948)

• C. Chen, D. Saraswat, R. Achar, E. Gad, M. Nakhla and M. C. E. Yagoub, A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs with FD-PUL Parameters Using Integrated Congruence Transform (3774)

• Chaeho Chung, Soobum Lee, Byung Man Kwak, Gawon Kim and Joungho Kim, A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm (3929)

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April 2008

Keynote Paper

• David Blaauw, Kaviraj Chopra, Ashish Srivastava and Lou Scheffer, Statistical Timing Analysis: From basic principles to state-of-the-art (3636)

Special Section on 2007 International Symposium on Physical Design (ISPD)

• P.H. Madden and D.Z.Pan, Guest Editorial - Special Section on 2007 International Symposium on Physical Design

• Vishal Khandelwal and Ankur Srivastava, Variability-Driven Formulation for Simultaneous Gate Sizing and Post-Silicon Tunability Allocation (4071)

• Hua Xiang, Kai-Yuan Chao, Ruchir Puri and Martin D.F. Wong, Is Your Layout Density Verification Exact ? --- A Fast Exact Deep Submicron Density Calculation Algorithm (4006)

• Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao and Martin D.F. Wong, Fast Dummy Fill Density Analysis with Coupling Constraints (4140)

• Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang and Chia-Lin Yang, Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs (4026)

• Tung-Chieh Chen, Yi-Lin Chuang and Yao-Wen Chang, Effective Wire Models for X-Architecture Placement (4141)

Regular Issue

• Cheoljoo Jeong and Steven M. Nowick, Technology Mapping and Cell Merger for Asynchronous Threshold Networks (3837)

• Neil Kettle and Andy King, An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs (3872)

• Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He and Xianlong Hong, Fashion: A Fast and Accurate Solution to Global Routing Problem (3808)

• Seok-Won Seong and Prabhat Mishra, Bitmask-Based Code Compression for Embedded Systems (4052)

• Ying Wei and Alex Doboli, Structural Macromodeling of Analog Circuits through Model Decoupling and Transformation (4032)

• Ryan Fung, Vaughn Betz and William Chow, Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations (3969)

• Abusaleh M. Jabir, and Dhiraj K. Pradhan and Jimson Mathew, GfXpress: A Technique for Synthesis and Optimization of GF(2^m) Polynomials (3953)

• Cheng Zhuo, Jiang Hu, Min Zhao and Kangsheng Chen, Power Grid Analysis and Optimization Using Algebraic Multigrid (3950)

• D. Maslov, S. M. Falconer and M. Mosca, Quantum Circuit Placement (4154)

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May 2008

• Claudio Pinello, Luca P. Carloni and Alberto L. Sangiovanni-Vincentelli, Fault-Tolerant Distributed Deployment of Embedded Control Software (3952)

• Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai and Janusz Rajski, Improving the Resolution of Single Delay Fault Diagnosis (4096)

• Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen and Brian Han, Full-Chip Gridless Routing Considering Double-Via Insertion (3947)

• Minsik Cho, Hua Xiang, Ruchir Puri and David Z. Pan, TROY: Track Routing and Optimization for Yield (4075)

• Irith Pomeranz and Sudhakar M. Reddy, On the Saturation of n-Detection Test Generation by Different Definitions with Increased n (4216)

• Natasa Miskov-Zivanov and Diana Marculescu, Modeling and Optimization for Soft-Error Reliability of Sequential Circuits (4065)

• Song Chen and Takeshi Yoshimura, Fixed-Outline Floorplanning: Block Position Enumeration and a New Method for Calculating Area Costs (4178)

• Bo Hu and C.-J. Richard Shi, Simulation of Closely-Related Dynamic Nonlinear Systems with Application to Process-Voltage-Temperature Corner Analysis (4055)

• Erkan Acar and Sule Ozev, Defect Oriented Testing of RF Circuits (4168)

• Shweta Srivastava and Jaijeet Roychowdhury, Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations (4045)

• Diana Marculescu and Siddharth Garg, Process-Driven Variability Analysis for Single and Multiple Voltage-Frequency Island, Latency-Constrained Systems (4127)

• Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya and C.-J. Richard Shi, Parasitic-Aware Optimization and Retargeting of Analog Layouts: a Symbolic Template Approach (4035)

• Paolo Maffezzoni, Unified Computation of Parameter-Sensitivity and Signal-Injection Sensitivity in Nonlinear Oscillators (4005)

• Xin Li, Yaping Zhan and Lawrence Pileggi, Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits (4105)

Short Papers:

• Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty and Zebo Peng, Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling (4051)

• Bhaskar Pal, Ansuman Banerjee, Arnab Sinha and Pallab Dasgupta, Accelerating Assertion Coverage with Adaptive Test-benches (4149)

• Gulin Tulunay and Sina Balkir, A Synthesis Tool for CMOS RF Low Noise Amplifiers (4111)

• X. Ma and F. Lombardi, Synthesis of Tile Sets for DNA Self-Assembly (4025)

• Jeong-Ho Han and In-Cheol Park, FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient (4108)

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June 2008

• Chong-Fatt Law, Bah-Hwee Gwee and Joseph S. Chang, Asynchronous Control Network Optimization Using Fast Minimum Cycle Time Analysis (4011)

• Javid Jaffari and Mohab Anis, Statistical Thermal Profile Considering Process Variations: Analysis and Applications (4180)

• Goerschwin Fey and Stefan Staber and Roderick Bloem and Rolf Drechsler, Automatic Fault Localization for Property Checking (3735)

• Tarvo Raudvere, Ingo Sander and Axel Jantsch, Application and Verification of Local Non-Semantic-Preserving Transformations in System Design (4175)

• Saqib S. Khursheed, Urban Ingelsson, Paul Rosinger, Bashir M. Al-Hashimi and Peter Harrod, Bridging Fault Test Method with Adaptive Power Management Awareness (4167)

• Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu James Chien-Mo Li, Diagnosis of Multiple Scan Chain Timing (4206)

• Pramod Chandraiah and Rainer Doemer, Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Re-Coding (4131)

• Levent Aksoy, Eduardo Costa, Paulo Flores and Jose Monteiro, Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications (4120)

• Jarrod A. Roy and Igor L. Markov, High-performance Routing at the Nanometer Scale (4188)

• Xin Li, Jiayong Le, Mustafa Celik and Lawrence T. Pileggi, Defining Statistical Timing Sensitivity for Logic Circuits with Large-Scale Process and Environmental Variations (4056)

• Dong Xiang, Yang Zhao, Krishnendu Chakrabarty and Hideo Fujiwara, A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST (4210)

• Afshin Abdollahi and Massoud Pedram, Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions (4191)

• Zhe-Wei Jiang and Yao-Wen Chang An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing (4159)

Short Papers:

• Brajesh Kumar Kaushik and Sankar Sarkar, Crosstalk Analysis for a CMOS Gate Driven Coupled Interconnects (4209)

• Lin Yuan, Gang Qu, Tiziano Villa and Alberto Sangiovanni-Vincentelli, An FSM Re-Engineering Approach to Sequential Circuit Synthesis by State Splitting (4145)

• Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alex Nicolau, Yunheung Paek and Eugene Earlie, Register File Power Reduction Using Bypass Sensitive Compiler (4181)

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July 2008

• Lei Cheng, Deming Chen and Martin D. F. Wong, Delay-Driven BDD Synthesis for FPGAs (4190)

• Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski and Jerzy Tyszer, Low Power Test Data Application in EDT Environment through Decompressor Freeze (4333)

• Andrew B. Kahng, Puneet Sharma and Rasit O. Topaloglu, Chip Optimization Through STI Stress-Aware Placement Perturbations and Fill Insertion (4184)

• Yiyu Shi, Jinjun Xiong, Chunchen Liu and Lei He, Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations (4330)

• Daniel Grosse, Ulrich Kuehne and Rolf Drechsler, Analyzing Functional Coverage in Bounded Model Checking (4153)

• Soner Yaldiz, Alper Demir and Serdar Tasiran, Stochastic Modeling and Optimization for Energy Management in Multi-Core Systems: A Video Decoding Case Study (4118)

• R. Castro-López, O. Guerra, E. Roca, and Francisco V. Fernández, An Integrated Layout-Synthesis Approach for Analog ICs (4306)

• Anna Bernasconi, Valentina Ciriani, Rolf Drechsler and Tiziano Villa, Logic Minimization and Testability of 2-SPP Networks (4067)

• Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen and Yao-Wen Chang, NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs with Preplaced Blocks and Density Constraints (4001)

• Vijay D'Silva, Daniel Kroening and Georg Weissenbacher, A Survey of Automated Techniques for Formal Software Verification (3968)

• Taehoon Kim and Yungseon Eo, Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multi-Coupled RLC Interconnect Lines (4264)

• Sari Onaissi and Farid N. Najm, A Linear-Time Approach for Static Timing Analysis Covering All Process Corners (4259)

• Xiaoxi Xu and Cheng-Chew Lim, Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip (4255)

Short Papers:

• Jing-ling Yang and Qiang Xu, State-Sensitive X-filling Scheme for Scan Capture Power Reduction (4359)

• Rolf Drechsler, Stephan Eggersgluess, Goerschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel and Daniel Tille, On Acceleration of SAT-based ATPG for Industrial Designs (4307)

• Hao Zheng, Jared Ahrens and Tian Xia, A Compositional Method with Failure-Preserving Abstraction for Asynchronous Design Verification (4287)

• X. Kavousianos, E. Kalligeros and D. Nikolos, Test-Data Compression Based on Variable-to-Variable Huffman Encoding with Codeword Reusability (4282)

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August 2008

• Peter Spindler, Ulf Schlichtmann and Frank M. Johannes, Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model (4313)

• Ozgur Sinanoglu and Tsvetomir Petrov, Isolation Techniques for Soft Cores (4418)

• Ilya Issenin, Erik Brockmeyer, Bart Durinck and Nikil Dutt, Data Reuse Driven Energy-Aware Co-Synthesis of Scratch Pad Memory and Hierarchical Bus Based Communication Architecture for Multiprocessor Streaming Applications (4280)

• Changyun Zhu, Zhenyu Gu, Li Shang, Robert P. Dick and Russ Joseph, Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management (4410)

• Chih-Hung Liu, Hung-Yi Liu, Chung-Wei Lin, Szu-Jui Chou, Yao-Wen Chang, Sy-Yen Kuo, Shih-Yi Yuan and Yu-Wei Chen, An Efficient Graph-Based Algorithm for ESD Current Path Analysis (4261)

• Jason Cong IEEE Fellow and Min Xie, A Robust Mixed-Size Legalization and Detailed Placement Algorithm (4402)

• Changjiu Xian, Yung-Hsiang Lu and Zhiyuan Li, Dynamic Voltage Scaling for Multitasking Real-Time Systems with Uncertain Execution Time (4236)

• Giovanni Agosta, Francesco Bruschi and Donatella Sciuto, Static Analisys of Transaction Level Communication Models (4395)

• Uday Padmanabhan,Janet M Wang and Jiang Hu, Robust Clock Tree Routing in the Presence of Process Variations (4164)

• Karam S. Chatha, Krishnan Srinivasan and Karam S. Chatha, Automated Techniques for Synthesis of Application Specific Network-on-Chip Architectures (3997)

• Maharaj Mukherjee and Kanad Chakraborty, A Randomized Greedy Method for Rectangular Pattern Fill Problem (4344)

Short Papers:

• Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta and Pranav Ashar, Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking (4227)

• Shuai Wang, Jie Hu and Sotirios G. Ziavras, Self-Adaptive Data Caches for Soft-Error Reliability (4382)

• Wenjian Yu, Xiren Wang, Zuochang Ye and Zeyi Wang, Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method (4347)

• Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan Mandal and Amit Patra, A Fast Exploration Procedure for Analog High-level Specification Translation (4335)

• King Ho Tam, Yu Hu, Lei He, Tom Tong Jing and Xinyi Zhang, Dual-Vdd Buffer Insertion for Power Reduction (4329)

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September 2008

• I. Vytyaz, D. C. Lee, P. K. Hanumolu, U.-K. Moon and K. Mayaram, Sensitivity Analysis for Oscillators (4427)

• H. Fujiwara, H. Iwata, T. Yoneda and C. Y. Ooi, A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models (4458)

• Y.-J. J. Yang and C.-W. Kuo, Generating Scalable and Modular Macromodels for Microchannels Using the Galerkin-Based Technique (4444)

• H. Hassan, M. Anis and M. Elmasry, Input Vector Reordering for Leakage Power Reduction in FPGAs (4482)

• U. Brenner, M. Struzyna and J. Vygen, BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms (4468)

• A. Cui, C.-H. Chang and S. Tahar, IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level (4277)

• Y.-T. Li, Z. Bai, Y. Su and X. Zeng, Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process (4297)

• H. Tennakoon and C. Sechen, Nonconvex Gate Delay Modeling and Delay Optimization (4456)

• C. Xu, R. Gharpurey, T. S. Fiez and K. Mayaram, Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method (4417)

• T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang and T.-Y. Liu, MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs (4399)

• A. B. Kahng, C.-H. Park and X. Xu, Fast Dual-Graph-Based Hotspot Filtering (4385)

• T.-H. Lee and T.-C. Wang, Congestion-Constrained Layer Assignment for Via Minimization in Global Routing (4374)

• M. Choi and L. Milor, Diagnosis of Optical Lithography Faults With Product Test Sets (4409)

• F.-C. Yang, W.-K. Huang, J.-K. Zhong and I.-J. Huang, Automatic Verification of External Interrupt Behaviors for Microprocessor Design (4356)

Short Papers:

• J.-C. Guo and Y.-M. Lin, A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs (4360)

• J. Kakade, D. Kagaris and D. K. Pradhan, Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs (4451)

• H.-C. Liang, P.-H. Huang and Y.-F. Tang, Testing Transition Delay Faults in Modified Booth Multipliers (4560)

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October 2008

• Jin Sun,Jun Li, Dongsheng Ma and Janet M. Wang, Chebyshev Affine Arithmetic Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty (4475)

• Kian Haghdad and Mohab Anis, Design-Specific Optimization Considering Supply and Threshold Voltage Variations (4470)

• Minsik Cho and David Z. Pan, A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips (4466)

• Chen-Ling Chou, Umit Y. Ogras and Radu Marculescu, Energy- and Performance-aware Incremental Mapping for Networks-on-Chip with Multiple Voltage Levels (4455)

• Osama Neiroukh, Stephen A. Edwards and Xiaoyu Song, Transforming Cyclic Circuits into Acyclic Equivalents (4452)

• Andrew Labun and Karan Jagjitkumar, Rapid, Detailed Temperature Estimation for Highly Coupled IC Interconnect (4563)

• Alessandro Cimatti, Marco Roveri and Stefano Tonetta, Symbolic Compilation of PSL (4438)

• Nishant Patil, Jie Deng, Albert Lin, H. -S. Philip Wong and Subhasish Mitra, Design Methods for Misaligned and Mis-positioned Carbon-Nanotube Immune Circuits (4495)

• Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak and Majid Sarrafzadeh, General Methodology for Soft Error-Aware Power Optimization using Gate Sizing (4352)

• Guo Yu, Wei Dong, Zhuo Feng and Peng Li, Statistical Static Timing Analysis Considering Process Variation Model Uncertainty (4489)

• Ajay K. Verma, Philip Brisk and Paolo Ienne, Data-Flow Transformations to Maximise the Use of Carry-Save Representation in Arithmetic Circuits (4346)

• Khaled R. Heloue and Farid N. Najm, Early Analysis and Budgeting of Margins and Corners using Two-sided Analytical Yield Models (4484)

• Ehsan Pakbaznia, Farzan Fallah and Massoud Pedram, Charge Recycling in Power-Gated CMOS Circuits (4319)

• Yu Hu, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetries to Speed-Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs (4477)

• Wayne Wolf, Ahmed A. Jerraya and Grant Martin, Multiprocessor System-on-Chip (MPSoC) Technology (4185)

• Sarvesh Bhardwaj, Sarma Vrudhula and Amit Goel, A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations (4476)

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November 2008

• Seda Ogrenci Memik, Nikolaos Bellas and Somsubhra Mondal, Pre-synthesis Area Estimation of Reconfigurable Streaming Accelerators (4620)

• Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li and Yao-Wen Chang, Multi-Layer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs (4526)

• M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici and Giovanni De Micheli, Variability-Aware Design of Multi-Level Logic Decoders for Nanoscale Crossbar Memories (4524)

• Seongmoon Wang and Wenlong Wei, An Efficient Unknown Blocking Scheme for Low Control Data Volume and High Observability (4514)

• Ping-Hung Yuh, Chia-Lin Yang, and Yao-Wen Chang, BioRoute: A Network-Flow Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips (4598)

• Ning Mi, Sheldon Tan, Yici Cai and Xianlong Hong, Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method (4511)

• Tao Xu and Krishnendu Chakrabarty, A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips (4500)

• Michael D. Moffitt, MaizeRouter: Engineering an Effective Global Router (4567)

• Minh D. Nguyen, Max Thalmaier, Markus Wedler, Dominik Stoffel and Wolfgang Kunz, Unbounded Protocol Compliance Verification using (4463)

• Mohamed Abu-rahma and Mohab Anis, A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations (4555)

• Yongsoo Joo, Yongseok Choi, Jaehyun Park, Chanik Park, Sung Woo Chung, Eui-Young Chung and Naehyuck Chang, Energy and Performance Optimization of Demand Paging with OneNAND Flash (4429)

• Jun Seomun, Jae-hyun Kim and Youngsoo Shin, Skewed Flip-Flop and Mixed-Vt Gates for Minimizing Leakage in Sequential Circuits (4421)

• Yung-Chih Chen and Chun-Yao Wang, An Implicit Approach to Minimizing Range-Equivalent Circuits (4529)

Short Papers:

• HyunJin KIM, Hyejeong Hong, Hong-Sik Kim, Jin-Ho Ahn and Sungho Kang, Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor using Dynamic Voltage Scaling Efficiency Metric (4608)

• Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey,Liang-Chia Cheng, Ji-Jan Chen and Wen-Ching Wu, Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits (4604)

• Ho Fai Ko and Nicola Nicolici, Automated Scan Chain Division for Reducing Shift and Capture Power during Broadside At-Speed Test (4568)

• Sertac Cinel and Cuneyt F. Bazlamacci, A Distributed Heuristic Algorithm for the Rectilinear Steiner Tree Problem (4534)

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December 2008

Special Section on the 2008 International Symposium on Physical Design (ISPD)

• Stephen M Plaza, Igor L Markov and Valeria Bertacco, Optimizing Non-Monotonic Interconnect using Functional Simulation and Logic Restructuring (4665)

• Hosung (Leo) Kim and John Lillis, A Layout-Level Logic Restructuring Framework for LUT-based FPGAs (4662)

• Jason Cong and Guojie Luo, Highly Efficient Gradient Computation for Density-Constrained Analytical Placement (4657)

• Tung-Chieh Chen, Minsik Cho, David Z. Pan and Yao-Wen Chang, Metal-Density Driven Placement for CMP Variation and Routability (4650)

• David A. Papa, Tao Luo, Michael D. Moffitt, C. N. Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert and Igor L. Markov, RUMBLE: An Incremental, Timing-driven, Physical-synthesis Optimization Algorithm (4655)

• Jieyi Long, Hai Zhou and Seda Ogrenci Memik, EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm (4630)

• Yifang Liu, Jiang Hu and Weiping Shi, Buffering Interconnect for Multi-Core Processor Designs (4653)

• Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh and Kai-Yuan Chao, Fast and Optimal Redundant Via Insertion (4651)

Regular Issue

• Tobias Massier, Helmut Graeb and Ulf Schlichtmann, The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis (4497)

• D. Walter, S. Little, C. Myers, N. Seegmiller and T. Yoneda, Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods (4551)

• Tomasz S. Czajkowski and Stephen D. Brown, Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs (4601)

• Roxana Ionutiu, Joost Rommes and Athanasios C. Antoulas, Passivity preserving model reduction using dominant spectral zero interpolation (4611)

• Lin Xie and Azadeh Davoodi, Robust estimation of timing yield with partial statistical information on process variations (4518)

• Rebecca L. Collins and Luca P. Carloni, Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems (4640)

• Chunrong Song and Spyros Tragoudas, Identification of Critical Executable Paths at the Architectural Level (4544)

• Ozgur Sinanoglu, Scan Architecture with Align-Encode (4771)

• Amith Singhee, Claire F. Fang, James D. Ma and Rob A. Rutenbar, Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools (4479)

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