January 2007

• Zai-Fa Zhou, Qing-An Huang, Wei-Hua Li and Wei Lu, A Novel 3-D Dynamic Cellular Automata Model for Photoresist Etching Process (2735)

• Xin Li, Jiayong Le, Padmini Gopalakrishnan and Lawrence T. Pileggi, Asymptotic Probability Extraction for Non-Normal Performance Distributions (3060)

• Xin Li, Padmini Gopalakrishnan, Yang Xu and Lawrence T. Pileggi, Robust Analog/RF Circuit Design with Projection-Based Performance Modeling (3019)

• C. Chiang, A. B. Kahng, S. Sinha and X. Xu, Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction (2994)

• Akhilesh Kumar and Mohab Anis, Dual Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs (2993)

• Kai-hui Chang, Valeria Bertacco and Igor L. Markov, Simulation-based Bug Trace Minimization with BMC-based Refinement (2988)

• Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee and Gabriel H. Loh, Multi-Objective Microarchitectural Floorplanning For 2D And 3D ICs (3162)

• Yonghong Yang, Zhenyu (Peter) Gu, Changyun Zhu, Robert P. Dick and Li Shang, ISAC: Integrated Space and Time Adaptive Chip-Package Thermal Analysis (2966)

• Devang Jariwala and John Lillis, RBI: Simultaneous Placement and Routing Optimization Technique (2659)

• Ashish Srivastava, Tejasvi Kachru and Dennis Sylvester, Low-Power Design Space Exploration Considering Process Variation using Robust Optimization (3157)

• Taewhan Kim and Jungeun Kim, Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory Access Optimization (3123)

• Shinji Odanaka, A high-resolution method for quantum confinement transport simulations in MOSFETs (3121)

Short Papers:

• Kyosun Kim, Kaijie Wu and Ramesh Karri, The Robust QCA Adder Designs using Composable QCA Building Blocks (3218)

• Dipanjan Sengupta and Resve Saleh, Generalized Power-Delay Metrics in Deep Submicron CMOS Designs (2847)

• Wendemagegnehu (Wendem) Beyene, Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Spe (2814)

• B. K. S. V. L. Varaprasad, L. M. Patnaik, H. S. Jamadagni and V. K. Agrawal, A New ATPG Technique (ExpoTan) for Testing Analog Circuits (2784)

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February 2007

• Jason Cong and Kirill Minkovich, Optimality Study of Logic Synthesis for LUT-Based FPGAs (3399)

• Kedarnath J. Balakrishnan and Nur A. Touba, Relationship Between Entropy and Test Data Compression (3209)

• Russell Tessier, Vaughn Betz, David Neto, Aaron Egier and Thiagaraja, Power-efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks (3318)

• Baohua Wang and Pinaki Mazumder, Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function (3154)

• Alan Mishchenko, Satrajit Chatterjee and Robert Brayton, Improvements to Technology Mapping for LUT-Based FPGAs (3299)

• A. B. Kahng, I. I. Mandoiu, X Xu and A. Z. Zelikovsky, Enhanced Design Flow and Optimizations for Multi-Project Wafers (3096)

• Xiaoyong Chen, Douglas Maskell and Yang Sun, Fast Identification of Custom Instructions for Extensible Processors (3278)

• Dongkun Shin and Jihong Kim, Optimizing Intra-Task Voltage Scheduling Using Profile and Data Flow Information (2898)

• Ismail Kadayif, Partho Nath, Mahmut Kandemir and Anand Sivasubramaniam, Reducing Data Tlb Power via Compiler-Directed Address Generation (2888)

• Peter Yiannacouras, J. Gregory Steffan and Jonathan Rose, Exploration and Customization of FPGA-Based Soft Processors (3269)

• Yih-Lang Li, Jin-Yih Li and Wen-Bin Chen, An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow (2883)

• Welson Sun, Michael J. Wirthlin and Stephen Neuendorffer, FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource (3260)

• Mingjie Lin, Abbas El Gamal, Yi-Chang Lu and Simon Wong, Performance Benefits of Monolithically Stacked 3D-FPGA (3258)

• Ian Kuon and Jonathan Rose, Measuring the Gap Between FPGAs and ASICs (3255)

Short Papers:

• Jinkyu Lee and Nur A. Touba, LFSR Reseeding Scheme Achieving Low Power Dissipation During Test (2930)

• Mark Holland and Scott Hauck, Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC (3271)

• Tim Tuan, Arif Rahman, Satyaki Das and Steve Trimberger, A 90nm Low-Power FPGA for Battery-Powered Applications (3270)

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March 2007

Special Section on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference

• Partha Biswas, Nikil Dutt, Laura Pozzi and Paolo Ienne, Introduction of Architecturally Visible Storage in Instruction Set Extensions (3455)

• Arindam Mallik, Debjit Sinha, Hai Zhou and Prith Banerjee, Low Power Optimization by Smart Bit-width Allocation in a SystemC based ASIC Design Environment (3422)

• Cristian Soviani, Olivier Tardieu and Stephen A. Edwards, Optimizing Sequential Cycles through Shannon Decomposition and Retiming (3346)

• Federico Angiolini, Paolo Meloni, Salvatore Carta, Luigi Raffo and Luca Benini, A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs (3327)

• Rajeev R. Rao, Kaviraj Chopra, David Blaauw and Dennis Sylveste, Computing the Soft Error Rate of a Combinational Logic Circuit using Parameterized Descriptors (3324)

• Ying Wei, Alex Doboli and Hua Tang, Systematic Methodology for Designing Reconfigurable $Delta Sigma$ Modulator Topologies for Multimode Communication Systems (3322)

• Sudeep Pasricha and Nikil Dutt, A Framework for Co-synthesis of Memory and Communication Architectures for MPSoC (3254)

Short Papers:

• E. Giunchiglia, M. Narizzano and A. Tacchella, Quantifier structure in search based procedures for QBFs (3342)

Regular Issue

• Farid N. Najm, Noel Menezes and Imad A. Ferzli, A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis (3013)

• Mehdi B. Tahoori and Subhasish Mitra, Application-Dependent Delay Testing of FPGAs (3104)

• Chao-Yang Yeh and Malgorzata Marek-Sadowska, Timing-aware power noise reduction in placement (3184)

• Curtis A. Nelson, Chris J. Myers and Tomohiro Yoneda, Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits (3111)

• Anish Muttreja, Anand Raghunathan, Srivaths Ravi and Niraj K. Jha, Automated Energy/Performance Macromodeling of Embedded Software (3011)

• Li Shang, Robert P. Dick and Niraj K. Jha, SLOPES: Hardware-Software Co-Synthesis of Low-Power Real-Time Distributed Embedded Systems with Dynamic (2435)

• Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, and Allen C.-H. Wu, Performance-Driven Crosstalk Elimination at Post-Compiler Level - The Case of Low Crosstalk Op-code (2978)

Short Papers:

• B.P. Harish, Navakanta Bhat and Mahesh B. Patil, On A Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance (2956)

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April 2007

Special Section on 2006 International Symposium on Physical Design (ISPD)

• Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Yang, Vijay Pitchumani and Chung-Kuan Cheng, Efficient Thermal Via Planning Approach And Its Application In Ther-mal-oriented 3D Floorplanning (3286)

• Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan and Xianlong Hong, Pattern Based Iterative Method for Extreme Large Power/Ground Analysis (3463)

• Jinjun Xiong, Vladimir Zolotov and Lei He, Robust Extraction of Spatial Correlation (3223)

• Jianhua Li, Laleh Behjat and Andrew Kennings, Net Cluster: A Net-Reduction Based Clustering Preprocessing Algorithm for Partitioning and Placement (3445)

• Shinichi Koda, Chikaaki Kodama and Kunihiro Fujiyoshi, Linear Programming-Based Cell Placement with Symmetry Constraints for Analog IC Layout (3392)

• Jarrod A. Roy and Igor L. Markov, Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement (3373)

• Yih-Lang Li, Hsin-Yu Chen and Chih-Ta Lin, NEMO: A New Implicit Connection Graph-Based Gridless Router with Multi-Layer Planes and Pseudo-Tile Propagation (3365)

• Chen-Wei Liu and Yao-Wen Chang, Power/Ground Network and Floorplan Co-Synthesis for Fast Design Convergence (3310)

• Bor-Yiing Su, Yao-Wen Chang and Jiang Hu, An Exact Jumper Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles (3297)

Short Papers:

• Jinjun Xiong and Lei He, Probabilistic Transitive-closure Ordering and its Application on Variational Buffer Insertion (3429)

• Jun Chen and Lei He, Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity (3357)

Regular Issue

• B. Lasbouygues, R. Wilson, N. Azemard and P. Maurine, Temperature and Voltage Aware Timing Analysis (2991)

• Hiren D. Patel, Sandeep K. Shukla and Reinaldo Bergamaschi, Heterogeneous Behavioral Hierarchy Extensions for SystemC (2982)

• Bipul C Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam and Kaushik Roy, Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits (2822)

• Fei Li, Yan Lin and Lei He Field Programmability of Supply Voltages for FPGA Power Reduction (3159)

• Benny Thörnberg, Martin Palkovic, Qubo Hu, Leif Olsson, Per Gunnar Kjeldsberg, Mattias O'Nils and Francky Catthoor, Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems (3134)

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May 2007

• Yung-Chieh Lin, Feng Lu and Kwang-Ting Cheng, Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation (3100)

• Zhengyong Zhu, He Peng, Khosro Rouz, Manjit Borah,Chung-Kuan Cheng and Ernest S. Kuh, Two-Stage Newton-Raphson Method for Transistor Level Simulation (3095)

• Jin-Fu Li, Testing Ternary Content Addressable Memories with Comparison Faults Using March-Like Tests (3307)

• Lei He, Andrew Kahng, King Ho Tam and Jinjun Xiong, Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation (3001)

• Nisar Ahmed, Mohammad Tehranipoor, C.P. Ravikumar and Ken Butler, Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers (2987)

• Chen He and Margarida Jacome, Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics (3215)

• Zhuo Li, Ying Zhou and Weiping Shi, Wie Sizing for Non-Tree Topology (2979)

• Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong and Patrick H. Madden, Routability-Driven Placement and White Space Allocation (2900)

• Shuo Zhou , Bo Yao, Hongyu Chen, Yi Zhu, Mike Hutton, Truman Collins, Sridhar Srinivasan, Nanchi Chou, Peter Suaris and Chung-Kuan Cheng, Efficient Timing Analysis with Known False Paths Using Biclique Covering (3168)

• Mohammad Tehranipoor and Reza M. P. Rad, Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based NanoFabrics (3116)

• Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, Mikhail Grinchuk and Arun Gunda, Scan Test Cost and Power Reduction through Systematic Scan Reconfiguration (3113)

• Martin Saint-Laurent, A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures (3110)

Short Papers:

• M.M.Vaseekar Kumar and S.Tragoudas, High Quality Transition Fault ATPG for Small Delay Defects (3264)

• Saihua Lin, Huazhong Yang and Rong Luo, A Novel rd/n RLCG Transmission Line Model Considering Complex RC (L) Loads (3177)

• Srinivasa R Sridhara and Naresh R Shanbhag, Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes (2895)

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June 2007

• Ting Mei and Jaijeet Roychowdhury, Small-Signal Analysis of Oscillators Using Generalized Multitime Partial Differential Equations (3139)

• Tai-Chen Chen and Yao-Wen Chang, Multilevel Full-Chip Gridless Routing with Applications to Optical Proximity Correction (3070)

• Xrysovalantis Kavousianos, Emmanouil Kalligeros and Dimitris Nikolos, Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores (3352)

• Youngjin Cho and Naehyuck Chang, Energy-Aware Clock Frequency Assignment in Microprocessors and Memory Devices for Dynamic Voltage Scaling (3329)

• Ilya Wagner, Valeria Bertacco and Todd Austin, Microprocessor Verification via Feedback-Adjusted Markov Models (3063)

• Danil Sokolov, Alex Bystrov and Alex Yakovlev, Direct mapping of low-latency asynchronous controllers from STGs (3304)

• Emre Salman, Ali Dasdan, Feroze Taraporevala, Kayhan Kucukcakar and Eby G. Friedman, Exploiting Setup - Hold Time Interdependency In Static Timing Analysis (3285)

• Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou and Cheng-Wen Wu, Flash Memory Testing and Built-In Self-Diagnosis with March-Like Test Algorithms (2812)

• Wei Pei, Wen-Ben Jone and Yi-Ming Hu, Fault Modeling and Detection for Drowsy SRAM Caches (3242)

• Gang Wang, Wenrui Gong, Brian DeRenzi and Ryan Kastner, Ant Colony Optimizations for Resource and Timing Constrained Operation Scheduling (3212)

Short Papers:

• Yi-Yu Liu and TingTing Hwang, Crosstalk-aware Domino Logic Synthesis (3069)

• Ming-e Jing, Yue Hao and Zhou Dian, A Novel Optimization Method for Parametric Yield: Uniform Design & Mapping Distance Algorithm (3003)

• Irith Pomeranz, Invariant States and Redundant Logic in Synchronous Sequential Circuits (3274)

• Jiong Luo and Niraj K. Jha, Power-efficient Scheduling for Heterogeneous Distributed Real-time Embedded Systems (2454)

• Changzhong Chen, Emad Gad, Michel Nakhla and Ram Achar, Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform (3207)

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July 2007

• Srinivasan Murali, Luca Benini and Giovanni De Micheli, An Application-Specific Design Methodology for On-Chip Crossbar Generation (3206)

• Namrata Shekhar, Priyank Kalla and Florian Enescu, Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing (3367)

• Rui Zhang, Pallav Gupta and Niraj K. Jha, Majority and Minority Network Synthesis with Application to QCA, SET and TPL Based NanotechnologiesMajority and Minority Network Synthesis with Application to QCA, SET and TPL Based Nanotechnologies (3353)

• Vishal Khandelwal and Ankur Srivastava, Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors (3130)

• Lili Zhou, Cherry Wakayama and C.-J. Richard Shi, CASCADE: A Standard Super-Cell Design Methodology with Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large Scale Integrated Circuits (3335)

• Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini and Giovanni De Micheli, Timing Error Tolerant Network-on-Chip Design Methodology (3109)

• Irith Pomeranz and Sudhakar M. Reddy, Generation of Broadside Transition Fault Test Sets that Detect Four-Way Bridging Faults (3321)

• Andrew C. Ling, Deshanand P. Singh and Stephen D. Brown, FPGA PLB Architecture Evaluation and Area Optimization Techniques using Boolean Satisfiability (2989)

• Chuan Lin and Hai Zhou, Trade-off between Latch and Flop for Min-Period Sequential Circuit Designs with Crosstalk (3306)

• Tomohiro Yoneda and Chris Myers, Synthesis of Timed Circuits based on Decomposition (3268)

• Huaizhi Wu, Martin D.F. Wong, I-Min Liu and Yusu Wang, Placement Proximity Based Voltage Island Grouping under Timing Requirement (3210)

• Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong and Lei He, Device and Architecture Co-Optimization for FPGA Power Reduction (3411)

Short Papers:

• Loganathan Lingappan and Niraj K. Jha, Efficient Design for Testability Solution based on Unsatisfiability for Register-transfer Level Circuits (3203)

• Shibaji Banerjee, Dipanwita Roy Chowdhury and Bhargab B. Bhattacharya, An Efficient Scan Tree Design for Compact Test Pattern Set (3253)

• C. N. Sze and Charles J. Alpert and Jiang Hu and Weiping Shi, Path Based Buffer Insertion (3248)

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August 2007

• Bernard N. Sheehan, Realizable Reduction of RC Networks (3474)

• Sudeep Pasricha, Nikil Dutt and Mohamed Ben-Romdhane, BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC (3245)

• Jia Wang and Hai Zhou, Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing (3430)

• Soroush Abbaspour, Hanif Fatemi and Massoud Pedram, Parameterized Non-Gaussian Variational Gate Timing Analysis (3239)

• Fang Liu and Sule Ozev, Statistical Test Development for Analog Circuits under High Process Variations (3416)

• M. Spevak and T.Grasser, Discretization of Macroscopic Transport Equations on Non-Cartesian Coordinate Systems (2751)

• Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang and Jyh-Herng Wang, A Network-Flow Based RDL Routing Algorithm for Flip-Chip Design (3401)

• Hsun-Cheng Lee, Yao-Wen Chang and Hannah H. Yang, MB*-tree: A Multilevel Floorplanner for Large-Scale Building-Module Design (2661)

• Debjit Sinha, Hai Zhou and Narendra V. Shenoy, Advances in Computation of the Maximum of a Set of Gaussian Random Variables (3389)

• Tai-Ying Jiang, Chien-Nan Jimmy Liu and Jing-Yang Jou, Observability Analysis on HDL Descriptions for Effective Functional Validation (3337)

• Yongseok Choi, Naehyuck Chang and Taewhan Kim, DC-DC Converter-Aware Power Management for Low-Power Embedded Systems (3334)

• Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang, Fault Diagnosis with Convolutional Compactors (3326)

• Pu Liu, Sheldon Tan, Bruce McGaughy, Lifeng Wu and Lei He, TermMerg: An Efficient Terminal Reduction Method for Interconnect Circuits (3256)

Short Papers:

• Qiang Xu, Nicola Nicolici and Krishnendu Chakrabarty, Test Wrapper Design and Optimization under Power Constraints for Embedded Cores with Multiple Clock Domains (3249)

• B. Linares-Barranco and T. Serrano-Gotarredona, On an Efficient CAD Implementation of the Distance Term in Pelgrom's Mismatch Model (3519)

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September 2007

• Gunar Schirner and Rainer Doemer, Result Oriented Modeling, a Novel Technique for Fast and Accurate TLM (3538)

• Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick and Hai Zhou, Unified Incremental Physical-Level and High-Level Synthesis (3410)

• Sanghamitra Roy, Weijen Chen, Charlie Chung-Ping Chen and Yu Hen Hu, Numerically convex forms and their application in gate-sizing (3536)

• Katherine Shu-Min Li, Yao-Wen Chang, C.-L. Lee, Chauchin Su and Jwu E. Chen, Multilevel Full-Chip Routing with Testability and Yield Enhancement (3400)

• Chang Woo Kang, Ali Iranli and Massoud Pedram, A Synthesis Approach for Coarse-grained, Antifuse-based FPGAs (3531)

• Peter Tummeltshammer, James C. Hoe and Markus Pueschel, Time-Multiplexed Multiple-Constant Multiplication (3330)

• Irith Pomeranz, Sudhakar M. Reddy and Srikanth Venkataraman, Z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs (3526)

• Yong Zhan and Sachin S. Sapatnekar, High Efficiency Green Function-Based Thermal Simulation Algorithms (3525)

• Maria C. Molina, Rafael Ruiz-Sautua, Jose M. Mendias and Roman Hermida, Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioural Synthesis (3484)

• A. Gerstlauer, D. Shin, J. Peng, R. Doemer and D. Gajski, Automatic, Layer-based Generation of System-On-Chip Bus Communication Models (3466)

• Chris Chu, Evangeline F. Y. Young, Dennis K. Y. Tong and Sampath Dechu, Wire Retiming Problem with Net Topology Optimization (3460)

• James D. Ma and Rob A. Rutenbar, Interval-Valued Reduced Order Statistical Interconnect Modeling (3456)

• Puneet Gupta, Andrew B. Kahng, Youngmin Kim and Dennis Sylvester, Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation (3293)

Short Papers:

• Ngai Wong and Venkataramanan Balakrishnan, Fast Positive-Real Balanced Truncation Via Quadratic Alternating Direction Implicit Iteration (3417)

• Sultan M. Al-Harbi, Fadel Noor and Fadi M. Al-Turjman, March DSS: A New Diagnostic March Test for All Memory Simple Static Faults (3026)

• Sung-Jin Cho, Un-Sook Choi, Han-Doo Kim, Yoon-Hee Hwang, Jin-Gyoung Kim and Seong-Hun Heo, New Synthesis of One-Dimensional 90/150 Linear Hybrid Group Cellular Automata (3597)

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October 2007

• Felice Balarin and Roberto Passerone, Specification, Synthesis and Simulation of Transactor Processes (3506)

• Love Singhal, Elaheh Bozorgzadeh and David Eppstein, Interconnect Criticality Driven Delay Relaxation (3495)

• Bo Yang and Ramesh Karri, Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique (3265)

• Anish Muttreja, Anand Raghunathan, Srivaths Ravi and Niraj K. Jha, Hybrid Simulation for Energy Estimation of Embedded Software (3108)

• Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Multi-Accuracy Power and Performance Transaction-Level Modeling (3473)

• Guido Stehr, Helmut Graeb and Kurt Antreich, Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination (3471)

• Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy and Muhammad Ashraful Alam, Impact of Negative Bias Temperature Instability in Nano-Scale SRAM Array: Modeling and Analysis (3634)

• Murari Mani, Anirudh Devgan, Michael Orshansky and Yaping Zhan, A Statistical Algorithm for Power- and Timing- Limited Parametric Yield Optimization of Large Integrated (3442)

• Sungjae Lee and Kevin J. Webb, A correlated diffusion noise model for the field-effect transistor (3602)

• Rashid Rashidzadeh, Majid Ahmadi and William C. Miller, Test and Measurement of Analog and RF Cores in Mixed-Signal SoC Environment (3556)

• Bor-Yiing Su and Yao-Wen Chang, An Optimal Jumper Insertion Algorithm for Antenna Avoidance/Fixing (3398)

Short Papers:

• Bao Liu, Xu Xu and Andrew B. Kahng, Statistical Timing Analysis in the Presence of Signal Integrity Effects (3378)

• Yu Cao and Lawrence T. Clark, Mapping Statistical Process Variations toward Circuit Performance Variability: An Analytical Modeling Approach (3317)

• Debdeep Mukhopadhyay, Gaurav Sengar and Dipanwita Roy Chowdhury, Hierarchical Verification of Galois Field Circuits (3493)

• Fei Xu, Chip-Hong Chang and Ching-Chuen Jong, Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients with Reusable Common Subexpressions (3259)

• Ja Chun Ku and Yehea Ismail, On the Scaling of Temperature-Dependent Effects (3488)

• Jayawant Kakade and Dimitri Kagaris, Minimization of Linear Dependencies through the Use of Phase Shifters (3433)

• Jin-Fu Li, Transparent Test Methodologies for Random Access Memories without/with ECC (3513)

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November 2007

• Eric Wong, Jacob Minz and Sung Kyu Lim, Decoupling Capacitor Planning and Sizing for Noise and Leakage Reduction (3621)

• Animesh Datta, Ashish Goel, Tamer Cakici, Hamid Mahmoodi, Dheepa Lekshmanan and Kaushik Roy, Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices (3543)

• Kazuo Aoyama, Design methods for symmetric function generators based on threshold elements (3608)

• Amitabh Chaudhary, Danny Z. Chen, X. Sharon Hu, Michael T. Niemier, Ramprasad Ravichandran and Kevin Whitton, Easing Fabricatable Interconnect in Molecular QCA Circuits (3527)

• Fei Sun, Srivaths Ravi, Anand Raghunathan and Niraj K. Jha, A Synthesis Methodology for Hybrid Custom Instruction and Co-processor Generation for Extensible Processors (3414)

• S. Manich, L. Garcia and J. Figueras, Minimizing Test Time in Arithmetic Test Pattern Generators with Constrained Memory Resources (3593)

• Sandip Aine, P. P. Chakrabarti and Rajeev Kumar, An Automated Meta-level Control Framework for Optimizing the Quality-Time Trade-off of VLSI Algorithms (3315)

• Swaroop Ghosh, Swarup Bhunia and Kaushik Roy, A New Paradigm for Low-power, Variation-Tolerant and Adaptive Circuit Synthesis Using Critical Path Isolation (3576)

• Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy and Kaushik Roy, Self-consistent Approach for Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits (3573)

• Markus Wedler, Dominik Stoffel, Raik Brinkmann and Wolfgang Kunz, A normalization method for arithmetic datapath verification (3554)

• Luca De Marchi, Emanuele Baravelli, Francesco Franze and Nicolo Speciale, Wavelet Adaptivity for 3D Device Simulation (3655)

• Juan A. López, Carlos Carreras and Octavio Nieto-Taladriz, Improved Interval-Based Characterization of Fixed-Point LTI Systems with Feedback Loops (3547)

• Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang Karandikar, Zhuo Li, Weiping Shi and C. N. Sze, Fast Algorithms For Slew Constrained Minimum Cost Buffering (3641)

Short Papers:

• Tong Jing, Zhe Feng, Yu Hu, Xianlong Hong, Xiaodong Hu and Guiying Yan, Lambda-OAT: Lambda-Geometry Obstacle-Avoiding Tree Construction with O(nlogn) Complexity (3545)

• Kai Yang and Kwang-Ting Cheng, Silicon Debug for Timing Errors (3606)

• Ruiming Chen and Hai Zhou, An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow (3572)

• Gaurav Sengar, Debdeep Mukhopadhyay, Dipanwita RoyChowdhury and Gaurav Sengar, Secured Flipped Scan Chain Model for Crypto-architecture (3749)

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December 2007

• Minsik Cho and David Z. Pan, BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP (3571)

• Puneet Gupta, Andrew B. Kahng and Chul-Hong Park, Detailed Placement for Enhanced Control of Resist and Etch CDs (3486)

• Bradley N Bond and Luca Daniel, A Piecewise-Linear Moment Matching Approach to Parameterized Model Order Reduction for Highly Nonlinear Systems (3698)

• Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil Dutt, Alex Nicolau and Yunheung Paek, Automatic Design Space Exploration of Register Bypasses in Embedded Processors (3676)

• Youngmin Yi, Dohyung Kim and Soonhoi Ha, Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization (3643)

• Wei Dong and Peng Li, Hierarchical Harmonic Balance Methods for Frequency-Domain Analog Circuits Analysis (3622)

• Jarrod A. Roy and Igor L. Markov, ECO-system: Embracing the Change in Placement (3736)

• Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul Villarrubia and Gi-Joon Nam, Diffusion-Based Placement Migration with Application on Legalization (3580)

• Cristian Grecu, André Ivanov, Resve Saleh and Partha P. Pande, Testing Network on Chip Communication Fabrics (3725)

Short Papers:

• Wen-Wen Hsieh, Po-Yuan Chen, Chun-Yao Wang and TingTing Hwang, A Bus Encoding Scheme for Crosstalk Elimination in High Performance Processor Design (3708)

• Sanghyeon Baeg, Delay Fault Coverage Enhancement by Partial Clocking For Low Power Designs with Heavily Gated Clocks (3594)

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