January 2006

• Wenjian Yu, Mengsheng Zhang and Zeyi Wang, Efficient 3-D Extraction of Interconnect Capacitance Considering Floating Metal-Fills with Boundary Element Method. (2084)

• Quming Zhou and Kartik Mohanram, Gate Sizing to Radiation Harden Combinational Logic. (2198)

• Jaewon Seo, Taewhan Kim, Ki-Seok Chung, Joonwon Lee, Optimal Intra-Task Dynamic Voltage Scaling and Its Practical Extensions. (1807)

• Arijit Raychowdhury and Kaushik Roy, Modeling of Metallic Carbon Nanotube Interconnects for Circuit Simulations and a Comparison with Cu Interconnects for Scaled Technologies. (2009)

• Kanad Chakraborty, Alexey Lvov, Maharaj Mukherjee, Novel Algorithms for Placement of Rectangular Covers for Mask Inspection in Advanced Lithography. (2180)

• Ying Zhang and Krishnendu Chakrabarty, A Unified Approach for Fault Tolerance and Dynamic Power Management in Fixed-Priority, Real Time Embedded Systems. (2047)

• Goerschwin Fey, Rolf Drechsler, Minimizing the Number of Paths in BDDs - Theory and Algorithm. (2134)

• Imad A. Ferzli and Farid N. Najm, Analysis and Verification of Power Grids Considering Process-Induced Leakage Current Variations. (2115)

• Maria C. Molina, Rafael Ruiz-Sautua, Jose M. Mendias, Roman Hermida, Bitwise Scheduling to Balance the Computational Cost of Behavioural Specifications. (2021)

• Josh Yang, Baosheng Wang, Yuejian Wu and Andre Ivanov, Fast Detection of Data Retention Faults and Other SRAM Cell Open Defects. (2058)

• Kyosun Kim, Ramesh Karri, Miodrag Potkonjak, Micro-Preemption Synthesis: An Enabling Mechanism for Multi-Task VLSI Systems. (2112)

• Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, and Rajendran Panda, Optimal Placement of Power Supply Pads and Pins. (2002)

• Qiang Xu and Nicola Nicolici, Multi-Frequency TAM Design for Hierarchical SOCs. (2097)

• Li Shang, Li-Shiuan Peh, Niraj K. Jha, PowerHerd: A distributed scheme for dynamically satisfying peak power constraints in interconnection networks. (1661)

• Jaijeet Roychowdhury and Robert Melville, Delivering Global DC Convergence for Large Mixed-Signal Circuits via Homotopy/Continuation Methods. (1509)

Short Papers:

• Shih-yu Yang and Christos A. Papachristou, A Method For Detecting Interconnect DSM Defects in Systems on Chip (SOCs). (2253)

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February 2006 -- Special Issue on Biochips

• Fei Su, Krishnendu Chakrabarty and Richard B. Fair, Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design Automation Challenges. (2397)

• Jun Zeng, Modeling and Simulation of Electrified Droplets and Its Application to Computer-Aided Design of Digital Microfluidics. (2404)

• Jan Lienemann, Andreas Greiner, and Jan G. Korvink, Modeling, Simulation and Optimization of Electrowetting. (2355)

• Xin Wang, Jacob White, Joe Kanapka, Wenjing Ye, Narayan Aluru, Algorithms in FastStokes and its application to micromachined device simulation. (2463)

• Yi Wang, Qiao Lin, Tamal Mukherje, Composable Behavioral Models and Schematic-Based Simulation of Electrokinetic Lab-on-a-Chips. (2457)

• Michael D. Altman and Jaydeep P. Bardhan, Bruce Tidor, Jacob K. White, FFTSVD: A Fast Multiscale Boundary Element Method Solver Suitable for BioMEMS and Biomolecule Simulation. (2458)

• Dmitry Vasilyev, Michal Rewienski, Jacob White, Macromodel generation for BioMEMS components using a stabilized Balanced Truncation plus Trajectory. (2512)

• A. S. Bedekar, Y. Wang, S. Krishnamoorthy, S. S. Siddhaye, and S. Sundaram, System-level simulation of flow induced dispersion in lab-on-a-chip systems. (2653)

• A.B. Kahng, I.I. Mandoiu, S. Reda, X. Xu, and A.Z. Zelikovsky, Computer-Aided Optimization of DNA Array Design and Manufacturing. (2475)

• Anton J. Pfeiffer, Tamal Mukherjee, and Steinar Hauan, Synthesis of Multiplexed Biofluidic Microchips. (2447)

• Karl F. Bohringer, Modeling and Controlling Parallel Tasks in Droplet-Based Microfluidic Systems. (2440)

• Eric J. Griffith, Srinivas Akella, Mark Goldberg, Performance Characterization of a Reconfigurable Planar Array Digital Microfluidic System. (2590)

• Sungroh Yoon, Luca Benini, Giovanni De Micheli, A Pattern Mining Method for High-throughput Lab-on-a-chip Data Analysis. (2441)

Short Papers:

• R. Magargle, J.F. Hoburg, T. Mukherjee, Microfluidic Injector Models Based On Artificial Neural Networks. (2464)

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March 2006

• Sangyun Kim, Peter A. Beerel, Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm. (1736)

• Muhammet Mustafa Ozdal and Martin D. F. Wong, An Algorithmic Study of Single-Layer Bus Routing for High-Speed Boards. (1916)

• Joonhwan Yi and John P. Hayes, High-level delay test generation for modular circuits. (2165)

• Kaijie Wu, Ramesh Karri, Algorithm Level RE-computing with Shifted Operands - A Register Transfer Level Concurrent Error Detection. (1851)

• Jason H. Anderson, Farid N. Najm, Active Leakage Power Optimization for FPGAs. (2064)

• Akshay Sharma, Carl Ebeling, Scott Hauck, PipeRoute: A Pipelining-Aware Router for Reconfigurable Architectures. (2181)

• Loganathan Lingappan, Srivaths Ravi, and Niraj K. Jha, Satisfiability based Test Generation for Non-separable RTL Controller-datapath Circuits. (2259)

• Dongkun Shin and Jihong Kim, Dynamic Voltage Scaling of Mixed Task Sets in Priority-Driven Systems. (2096)

• Navaratnasothie Selvakkumaran and George Karypis, Multi-Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization. (1850)

• Ruibing Lu and Cheng-Kok Koh, Performance Analysis of Latency Insensitive Systems. (2091)

• Hongmei Li,Cole E. Zemke, Giorgos Manetas, Vladimir I. Okhmatovski, Elyse Rosenbaum and Andreas C. Cangellaris, An automated and efficient substrate noise analysis tool. (2136)

• Zhuo Li and Weiping Shi, An $O(bn^2)$ Time Algorithm for Optimal Buffer Insertion with b Buffer Types. (2183)

• Zhiyuan Wang; Malgorzata Marek-Sadowska; Kun-Han Tsai; Janusz Rajski, Analysis and Methodology for the Multiple Fault Diagnosis. (2263)

• Andrew Kahng and Sherief Reda, New and Improved BIST Diagnosis Methods from Combinatorial Group Testing Theory. (2153)

• Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda, Verification of Timed Circuits with Failure Directed Abstractions. (2186)

Short Papers:

• Hua Tang, Alex Doboli, High-level Synthesis of Delta-Sigma Modulator Topologies Optimized for Complexity, Sensitivity and Performance. (2211)

• Irith Pomeranz and Sudhakar M. Reddy, Scan-BIST Based on Transition Probabilities for Circuits with Single and Multiple Scan Chains. (2122)

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April 2006 -- Special Issue on International Symposium on Physical Design 2005

• Qinghua Liu, Malgorzata Marek-Sadowska, Semi-individual Wire-Length Prediction with Application to Logic Synthesis. (2683)

• Rupesh S. Shelar, Prashant Saxena, and Sachin S. Sapatnekar, Technology Mapping Targeting Routing Congestion Under Delay Constraints. (2694)

• Tung-Chieh Chen and Yao-Wen Chang, Modern Floorplanning Based on B*-tree and Fast Simulated Annealing. (2713)

• Baris Taskin and Ivan S. Kourtev, Delay Insertion Method in Clock Skew Scheduling. (2685)

• Jaskirat Singh; Sachin Sapatnekar, A Partition-based Algorithm for Power Grid Design using Locality. (2704)

• Charles Alpert, Andrew Kahng, Gi-Joon Nam, Sherief Reda and Paul Villarrubia, A Fast Hierarchical Quadratic Placement Algorithm. (2703)

• Brent Goplen, Sachin S. Sapatnekar, Placement of Thermal Vias in 3D ICs using Various Thermal Objectives. (2721)

• James D. Ma and Rob A. Rutenbar, Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance. (2709)

• Yukiko Kubo and Atsushi Takahashi, Global Routing by Iterative Improvements for 2-Layer Ball Grid Array Packages. (2690)

Short Papers:

• Di Wu, Jiang Hu and Rabi Mahapatra, Antenna Avoidance in Layer Assignment. (2687)

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May 2006

Special Section on International Workshop on Logic Synthesis 2005

• Alan Mishchenko, Jin S. Zhang, Subarna Sinha, Jerry R. Burch, Robert Brayton and Malgorzata Chrzanowska-Jeske, Using Simulation and Satisfiability to Compute Flexibilities in Boolean Networks. (2566)

• Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein, Hardware Compilation of Application-Specific Memory Access Interconnect. (2743)

• Philip Brisk, Foad Dabiri, Majid Sarrafzadeh, Optimal Register Sharing for CFG Synthesis in SSA Form. (2754)

• Subramanian K Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain, On Partitioning and Symbolic Model Checking. (2758)

Short Papers:

• Tsutomu Sasao, Analysis and Synthesis of Weighted-Sum Functions. (2728)

Regular Issue

• Ying Yi and Roger Woods, Hierarchical Synthesis of Complex DSP Functions Using IRIS. (2227)

• Prem Menon, Weifeng Xu and Russell Tessier, Design Specific Path Delay Testing in Lookup Table-based FPGAs. (2264)

• Jaime Jiménez, José L. Martín, Member, IEEE, Aitzol Zuloaga, Unai Bidarte and Jagoba Arias, Comparison of two designs for the Multifunction Vehicle Bus. (2207)

• Yan Feng and Dinesh Mehta, Module Relocation to Obtain Feasible Constrained Floorplans. (2220)

• Haralampos-G. D. Stratigopoulos and Yiorgos Makris, Concurrent Detection of Erroneous Responses in Linear Analog Circuits. (2313)

• Srinivas Bodapati and Farid N. Najm, High-Level Current Macro-Model for Logic Blocks. (2095)

• Maged Ghoneima and Yehia Ismail, Formal Derivation of Optimal Active Shielding for Low-Power On-Chip Buses. (2229)

Short Papers:

• Kooho Jung, William R. Eisenstadt and Robert M. Fox, SPICE-Based Mixed-Mode S-Parameter Calculations for Four-Port and Three-Port Circuits. (2169)

• Ruediger Ebendt and Rolf Drechsler, The Effect of Improved Lower Bounds in Dynamic BDD Reordering. (2133)

• Kanak Agarwal, Dennis Sylvester and David Blaauw, Modeling and Analysis of Crosstalk Noise in Coupled RLC Interconnects. (2073)

• Chenggang Xu, Terri Fiez, and Karti Mayaram, An Error Control Method for Application of the Discrete Cosine Transform to Extraction of Substrate. (2056)

• Xun Liu, Yuantao Peng and Marios C. Papaefthymiou, Practical Repeater Insertion For Low Power: What Repeater Library Do We Need? (2249)

• Hong-Sik Kim and Sungho Kang, Increasing Encoding Efficiency of LFSR Reseeding Based Test Compression. (2302)

• Ewout Martens and Georges Gielen, Analyzing Continuous-Time Delta-Sigma Modulators With Generic Behavioral Models. (2315)

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June 2006

• Shih-Hsu Huang and Yow-Tyng Nieh, Synthesis of Non-Zero Clock Skew Circuits. (2128)

• Manan Syal and Michael S. Hsiao, New Techniques for Untestable Fault Identification in Sequential Circuits. (2177)

• Peter G. Sassone and Sung Kyu Lim, Traffic: A Novel Geometric Algorithm For Fast Wire-Optimized Floorplanning. (2203)

• Tao Jiang and R. D. (Shawn) Blanton, Inductive Fault Analysis of Surface-Micromachined MEMS. (2270)

• Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko and Jerry R. Burch, Linear Cofactor Relationships in Boolean Functions. (2233)

• Junjun Li, Sopan Joshi, Ryan Barnes and Elyse Rosenbaum, Compact Modeling of On-chip ESD Protection Devices Using Verilog-A. (2303)

• Zhao Li and C.-J. Richard Shi, SILCA: SPICE-Accurate Iterative Linear-Centric Analysis for Efficient Time-Domain Simulation of VLSI Circuits with Strong Parasitic Couplings. (2357)

• Debjit Sinha and Hai Zhou, Gate-Size Optimization under Timing Constraints for Coupling-Noise Reduction. (2141)

• Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Ku, Rajendran Panda and Chanhee Oh, Impact of Stress-Induced Backflow on Full-Chip Electromigration-Risk Assessment. (2297)

• Alan Mishchenko and Robert Brayton, A Theory of Non-Deterministic Networks. (2182)

• Vivek V. Shende, Stephen S. Bullock and Igor L. Markov, Synthesis of Quantum Logic Circuits. (2241)

• Sambuddha Bhattacharya, Nuttorn Jangkrajarng and C.-J. Richard Shi, Multi-Level Symmetry Constraint Generation for Retargeting Large Analog Layouts. (2278)

• Ravindra Jejurikar and Rajesh Gupta, Energy Aware Task Scheduling with Task Synchronization for Embedded Real-Time Systems. (2042)

Short Papers:

• Irith Pomeranz and Sudhaka M. Reddy, Transparent-DFT: A Design-for-Testability and Test Generation Approach for Synchronous Sequential Circuits. (2306)

• Cristinel Ababei, Hushrav Mogal and Kia Bazargan, Three-dimensional Place and Route for FPGAs. (2031)

• Lizheng Zhang, Weijen Chen, Yuhen Hu and Charlie Chungping Chen, Statistical Static Timing Analysis with Conditional Linear MAX/MIN Approximation and Extended Canoni. (2176)

• Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan and Ramesh Karri, Concurrent Error Detection for Involutional Functions with applications in Fault Tolerant Cryptograp. (2191)

• M. D. Galanis, G. Theodoridis, S. Tragoudas, and C.E. Goutis, A High-Performance Data-Path for Synthesizing DSP Kernels. (1999)

• A. Rajaram, J. Hu, R. Mahapatra and G. Venkataraman, Reducing Clock Skew Variability via Cross Links. (2187)

• Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stephane Donnay, Georges G.E. Gielen and Hugo J. De Man, Clock skew optimization methodology for substrate noise reduction with supply current folding. (2218)

• C. J. Alpert, J. Hu, S. S. Sapatnekar and C. N. Sze, Accurate Estimation of Global Buffer Delay within a Floorplan. (2312)

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July 2006

• Mongkol Ekpanyapong, Jacob Minz, Thaisiri Watewai, Hsien-Hsin Lee and Sung Kyu Lim, Profile-Guided Microarchitectural Floorplanning For Deep Submicron Processor Design (2111)

• Jongsun Park, Khurram Muhammad and Kaushik Roy, Efficient Modeling of 1/f^alpha Noise Using Multi-rate Process (2291)

• Laura Pozzi, Kubilay Atasu and Paolo Ienne, Exact and Approximate Algorithms for the Extension of Embedded Processor Instruction Set (2280)

• C. Umans, T.Villa and A. Sangiovanni-Vincentelli, Complexity of Two-Level Logic Minimization (2275)

• Saurabh N. Adya, Jarrod A. Roy, David A. Papa and Igor L. Markov, Min-Cut Floorplacement (2333)

• Kris Tiri and Ingrid Verbauwhede, A Digital Design Flow for Secure Integrated Circuits (2328)

• Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava and Miodrag Potkonjak, A Statistical Methodology for Wire-length Prediction (2188)

• Andrew B. Kahng and Sherief Reda, Wirelength Minimization for Min-Cut Placements via Placement Feedback (2323)

• Munkang Choi and Linda Milor, The Impact on Circuit Performance of Deterministic Within-Die Variation in Nanoscale Semiconductor Manufacturing (2132)

• Peng Rong and Massoud Pedram, Battery-Aware Power Management Based on Markovian Decision Processes (2314)

• Kanak Agarwal, Mridul Agarwal, Dennis Sylvester and David Blaauw, Statistical Interconnect Metrics for Physical Design Optimization (2131)

• Guoyong Shi, Bo Hu and C. -J. Richard Shi, On Symbolic Model Order Reduction (2308)

Short Papers:

• Dan Zhao, and Shambhu Upadhyaya and Martin Margala, Design of a Wireless Test Control Network with Radio-on-Chip Technology for Nanometer System-on-Chip (2283)

• Katarzyna Radecka and Zeljko Zilic, Arithmetic Transforms for Compositions of Sequential and Imprecise Datapaths (2383)

• Shibaji Banerjee, Debdeep Mukhopadhyay and Dipanwita Roy Chowdhury, An Integrated DFT Solution for Mixed Signal SOCs (2281)

• L. Knockaert and T. D'Haene, Orthonormal bandlimited Kautz sequences for global system modeling from piecewise rational models (2370)

• C. -J. Richard Shi, Michael. W. Tian and Guoyong Shi, Efficient DC Fault Simulation of Nonlinear Analog Circuits: One-Step Relaxation and Adaptive Simulatation Continuation (2349)

• Sampo Tuuna, Jouni Isoaho and Hannu Tenhunen, An Analytical Model for Crosstalk and Intersymbol Interference in Point-to-Point Buses (2262)

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August 2006

• Parivallal Kannan and Dinesh Bhatia, Interconnect Estimation for FPGAs (1994)

• Saibal Mukhopadhyay, Swarup Bhunia and Kaushik Roy, Modeling and Analysis of Loading Effect on Leakage of Nano-Scale Bulk-CMOS Logic Circuits (2419)

• Behzad Akbarpour and Sofiene Tahar, An Approach for the Formal Verification of DSP Designs using Theorem Proving (2412)

• Hua Tang, Hui Zhang and Alex Doboli, Refinement based Synthesis of Continuous-Time Analog Filters Through Successive Domain Pruning, Plat (2382)

• Puneet Gupta, Andrew B. Kahng, Puneet Sharma and Dennis Sylvester, Gate-Length Biasing for Runtime Leakage Control (2329)

• Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan and Lei He, Wideband Passive Multi-Port Model Order Reduction and Realization of RLCM Circuits (2318)

• Yung-Chieh Lin, Feng Lu and Kwang-Ting Cheng, Pseudo-Functional Testing (2557)

• Muhammet Mustafa Ozdal and Martin D. F. Wong, Algorithms for Simultaneous Escape Routing and Layer Assignment of Dense PCBs (2175)

• Hiren D. Patel, Deepak A. Matthaikutty, David Berner and Sandeep K. Shukla, CARH*: A Service Oriented Architecture for Validating System Level Designs (2507)

Short Papers:

• Sobeeh Almukhaizim and Yiorgos Makris and Petros Drineas, Entropy-Driven Parity Tree Selection for Low-Overhead Concurrent Error Detection in Finite State Machines (2482)

• Seongmoon Wang and Srimat T. Chakradhar, A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs (2389)

• Seongmoon Wang and Sandeep K. Gupta, LT-RTPG: A New Test-Per-Scan BIST TPG for Low Switching Activity (2388)

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September 2006

• Xiaoping Tang, Ruiqi Tian and Martin D.F. Wong, Minimizing Wire Length in Floorplanning (2309)

• Hua Xiang, Kai-Yuan Chao and Martin D.F. Wong, An ECO Routing Algorithm for Eliminating Coupling Capacitance Violations (2422)

• Xiangyin Zeng, Jiangqi He, Mostafa Abdulla and Qinglun Chen, Understanding and Closed-Form Formula Determination of Frequency Dependent Bonding Pad Characterization (2409)

• Peng Li, Lawrence Pileggi, Mehdi Asheghi and Rajit Chandra, IC Thermal Simulation and Modeling Via Efficient Multigrid-Based Approaches (2406)

• B. Lasbouygues, S. Engels, R. Wilson, P. Maurine, N. Azémard and D. Auvergne, Logical Effort Model Extension to Propagation Delay Representation (2403)

• Oskar Mencer, ASC: A Stream Compiler for Computing with FPGAs (2393)

• Fei Sun, Srivaths Ravi, Anand Raghunathan and Niraj K. Jha, Application-specific Heterogeneous Multiprocessor Synthesis using Extensible Processors (2379)

• Chuan Lin and Hai Zhou, Optimal Wire Retiming Without Binary Search (2639)

• Jun Chen and Lei He, Modeling and Synthesis of Multi-Port Transmission Line for Multi-Channel Communication (2544)

• Prashant Saxena, On Controlling Perturbation due to Repeaters during Quadratic Placement (2334)

• Hao Gang Wang, Chi Hou Chan, Leung Tsang and Vikram Jandhyala, On Sampling Algorithms in Multilevel QR Factorization Method for Magnetoquasistatic Analysis of Integrated Circuits over Multilayered Lossy Substrates (2471)

• Xiaohua Kong and Radu Negulescu, Semi-Hiding Operators and Active-Edge Specifications (2307)

• Annie Y. Zeng, Ken Rose and Ronald J. Gutmann, Memory Performance Prediction for High-Performance Microprocessors at Deep Submicron Technologies (2398)

• Arijit Mondal and P.P. Chakrabarti, Reasoning about Timing Behavior of Digital Circuits using Symbolic Event Propagation and Temporal Logic (2456)

• Rajeev R. Rao, Anirudh Devgan, David Blaauw and Dennis Sylvester, Analytical Yield Prediction Considering Leakage/Performance Correlation (2261)

• Bin Wu, Jianwen Zhu and Farid Najm, Dynamic Range Estimation (2396)

• William N. N. Hung, Xiaoyu Song, Guowu Yang, Jin Yang, and Marek Perkowski, Optimal Synthesis of Multiple Output Boolean Functions using a Set of Quantum Gates by Symbolic Reachability Analysis (2452)

• H. Y. Song, K. Nepal, R. I. Bahar, and J. Grodstein, Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations (2223)

• Jason Cong, Michail Romesis and Joseph R. Shinnerl, Fast Floorplanning by Look-Ahead Enabled Recursive Bipartitioning (2394)

• J. Carmona, J. M. Colom, J. Cortadella and F. Garcia Valles, Synthesis of Asynchronous Controllers using Integer Linear Programming (2431)

Short Papers:

• A. Rajaram, B. Lu, J. Hu, R. Mahapatra and W. Guo, Analytical Bound for Unwanted Clock Skew due to Wire Width Variation (2386)

• Ruiming Chen and Hai Zhou, Statistical Timing Verification for Transparently Latched Circuits (2371)

• Ruifeng Guo and Srikanth Venkataraman, An Algorithmic Technique for Diagnosis of Faulty Scan Chains (2500)

• Jens Vygen, Slack in Static Timing Analysis (2444)

• V. De La Luz, M. Kandemir and I. Kolcu, Reducing Memory Energy Consumption of Embedded Applications that Process Dynamically-Allocated Data (2413)

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October 2006

• Johann Cervenka, Wilfried Wessner, Elaf Al-Ani, Tibor Grasser and Siegfried Selberherr, Generation of Unstructured Meshes for Process and Device Simulation by Means of Partial Differential (2367)

• Lihong Zhang, Rabin Raut, Yingtao Jiang and Ulrich Kleine, Placement Algorithm in Analog Layout Designs (2538)

• Lin Zhong, Srivaths Ravi, Anand Raghunathan and Niraj K. Jha, RTL-aware Cycle-Accurate Functional Power Estimation (2359)

• Anup Hosangadi, Farzan Fallah and Ryan Kastner, Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination (2524)

• Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh and Tung-Sang Ng, Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction (2646)

• Sébastien Bilavarn, Guy Gogniat, Jean-Luc Philippe and Lilian Bossuet, Design space pruning through early estimations of area / delay trade-offs for FPGA implementations (2354)

• Dionysios Kouroussis, Rubil Ahmadi and Farid N. Najm, Voltage-Aware Static Timing Analysis (2521)

• Piet Engelke, Ilia Polian, Michel Renovell and Bernd Becker, Simulating Resistive Bridging and Stuck-At Faults (2707)

• Jae-Gon Lee and Chong-Min Kyung, PrePack: A Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-emulation (2519)

• Ming Zhang and Naresh R. Shanbhag, A Soft Error Rate Analysis (SERA) Methodology (2628)

• Andrew Kennings and Kristofer Vorwerk, Force-directed methods for generic placement (2701)

• C. Visweswariah, K. Ravindran, K. Kalafala, S. Walker, S. Narayan, D. Beece, J. Piaget, N. Venkateswaran and J. Hemmett, First-Order Incremental Block-Based Statistical Timing Analysis (2499)

• Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner and Eli Bozorgzadeh, Statistical Analysis and Design of HARP Routing Pattern FPGAs (2620)

• Yan Lin and Lei He, Dual-Vdd Interconnect with Chip-level Time Slack Allocation for FPGA Power Reduction (2679)

• Manish Verma, Lars Wehmeyer and Peter Marwedel, Cache Aware Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems (2102)

• Chao Huang, Srivaths Ravi, Anand Raghunathan and Niraj K. Jha, Use of Computation-unit Integrated Memories in High-level Synthesis (2616)

• Irith Pomeranz and Sudhakar M. Reddy, Using Dummy Bridging Faults to Define Reduced Sets of Target Faults (2676)

• J. Cortadella, A. Kondratyev, L. Lavagno and C. Sotiriou, De-synchronization: synthesis of asynchronous circuits from synchronous specifications (2461)

• Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha and Srimat T. Chakradhar, Test Volume Reduction in Systems-on-chip using Heterogeneous and Multi-level Compression Techniques (2609)

• Wilfried Wessner, Johann Cervenka, Andreas Hossinger and Siegfried Selberherr, Anisotropic Mesh Refinement for the Simulation of Three-Dimensional Semiconductor Manufacturing Processes (2671)

• Janet M. Wang, Hermite Polynomial based Interconnect Analysis in the Presence of Process Variations (2390)

• Prasenjit Basu, Sayantan Das, Ansuman Banerjee, Pallab Dasgupta, P.P. Chakrabarti, Chunduri Rama Mohan, Limor Fix and Roy Armoni, Design Intent Coverage -- A new paradigm for Formal Property Verification (2604)

• Saibal Mukhopadhyay, Keunwoo Kim, ChingTe Chuang, and Kaushik Roy, Modeling and Analysis of Leakage Currents in Double Gate Technologies (2669)

• Irith Pomeranz and Sudhakar M. Reddy, Generation of Functional Broadside Tests for Transition Faults (2559)

• Dong-U Lee, Altaf Abdul Gaffar, Ray C.C. Cheung, Oskar Mencer, Wayne Luk and George A. Constantinides, Accuracy Guaranteed Bit-Width Optimization (2736)

Short Papers:

• Qingwei Wu and Michael S. Hsiao, State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation (2651)

• Shu Yan, Vivek Sarin and Weiping Shi, Fast 3D Capacitance Extraction by Inexact Factorization and Reduction (2722)

• Shang-Wei Tu, Jing-Yang Jou and Yao-Wen Chang, RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction (2720)

• Bo Yang, Kaijie Wu and Ramesh Karri, Secure Scan: A Design-for-Test Architecture for Crypto Chips (2638)

• Jacob Minz and Sung Kyu Lim, Block-level 3D Global Routing With An Application to 3D Packaging (2346)

• M.-A. Cantin, Y. Savaria, D. Prodanos and P. Lavoie, A Metric for Automatic Word Length Determination of Hardware Datapaths (2293)

• Massimo Capobianchi, Simulating the Electrical Behavior of Integrated Circuit Devices in the Presence of Thermal Interactions (2472)

• Janet M. Wang, Satish Kumar, Jun Li Lakshmi, K Vakati and Kishore K Muchherla, Modeling the Driver-Load in the Presence Process Variations (2368)

• Valentina Ciriani, Anna Bernasconi and Rolf Drechsler, Testability of SPP Three-Level Logic Networks in Static Fault Models (2654)

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November 2006

• Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel and Fabio Somenzi, Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement (2733)

• Cheng-Tao Hsieh, Jian-Cheng Lin and Shih-Chieh Chang, A Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits (2689)

• Lizheng Zhang, Weijen Chen, John A. Gubner, Yuhen Hu and Charlie Chungping Chen, Correlation-Preserved Statistical Timing with Quadratic Form of Gaussian Variables (2776)

• J.A.G. Jess, K. Kalafala, S.R. Naidu, R.H.J.M. Otten and C. Visweswariah, Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits (2553)

• Erika Cota and Chunsheng Liu, Constraint-Driven Test Scheduling for NoC-based Systems (2724)

• Paolo Maffezzoni, Lorenzo Codecasa and Dario D'Amore, Event-Driven Time Domain Simulation of Closed-Loop Switched Circuits (2771)

• Petros Oikonomakos and Mark Zwolinski, An Integrated High-level On-line Test Synthesis Tool (2768)

• R. D. (Shawn) Blanton, K. N. Dwarakanath and R. Desineni, Defect Modeling using Fault Tuples (2695)

• Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee and Jwu E Chen, IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults (2765)

• Paul Rosinger, Bashir M. Al-Hashimi and Krisnendu Chakrabarty, Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits (2682)

• Liang Zhang, Indradeep Ghosh and Michael Hsiao, A Framework for Automatic Design Validation of RTL circuits using ATPG and Observability Enhanced Tag Coverage (2763)

• Nikolay Rubanov, A High Performance Subcircuit Recognition Method Based on the Nonlinear Graph Optimization (2909)

• Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai and Xianlong Hong, Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization (2680)

• Wai-Kei Mak and Chun-Lun Lai, On Constrained Pin Mapping for FPGA-PCB Co-Design (2760)

• Milos Hrkic, John Lillis and Giancarlo Beraudo, An Approach to Placement-Coupled Logic Replication (2808)

• Pallav Gupta, Abhinav Agrawal and Niraj K. Jha, An Algorithm for Synthesis of Reversible Logic Circuits (2806)

• Soheil Ghiasi, Elaheh Bozorgzadeh, Po-kuan Huang and Majid Sarrafzadeh, A Unified Theory of Timing Budget Management (2660)

• Irith Pomeranz and Sudhakar M. Reddy, Improved N-Detection Test Sequences Under Transparent-Scan (2745)

• Valavan Manohararajah, Stephen D. Brown, and Zvonko G. Vranesic, Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping (2780)

• Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay and Kaushik Roy, Modeling of Pipeline Delay and Statistical Design of Pipeline under Process Variation (2742)

Short Papers:

• Fang Liu, Sule Ozev and Martin Brooke, Identifying the Source of BW Failures in High Frequency Linear Analog Circuits Based on S-Parameter Measurements (2779)

• Hung-Ming Chen, I-Min Liu and Martin D.F. Wong, I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design (2623)

• Feng Gao and John P. Hayes, Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction (2515)

• Aiman H. El-Maleh, S. Saqib Khursheed and Sadiq M. Sait, Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation (2714)

• Yutao Hu and Kartikeya Mayaram, A Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation (2436)

• Nan-Cheng Lai, Sying-Jyan Wang and Yu-Hsuan Fu, Low Power BIST with Smoother and Scan-Chain Reorder under Optimal Cluster Size (2663)

• Pyoungwoo Min, Hyunbean Yi, Jaehoon Song, Sanghyeon Baeg and Sungju Park, Efficient Interconnect Test Patterns for Crosstalk and Static Faults (2753)

• D. Kagaris, P. Karpodinis and D. Nikolos, Maximum Length Sequences for Accumulator-Based Serial TPG (2647)

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December 2006

• L. Miguel Silveira and Joel R. Phillips, Resampling Plans for Sample Point Selection in Multipoint Model Order Reduction (2831)

• Hessa Al-Junaid, Tom Kazmierski, Peter Wilson and Jerzy Baranowski, Timeless Discretization of the Magnetization Slope in Modeling of Ferromagnetic Hysteresis (2702)

• Arthur Nieuwoudt and Yehia Massoud, Variability-Aware Multi-Level Integrated Spiral Inductor Synthesis (2894)

• Jingcao Hu, Umit Y. Ogras and Radu Marculescu, System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design (2838)

• Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak, Latency-Guided On-Chip Bus Network Design (2821)

• Andrew B. Kahng and Sherief Reda, Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking (2759)

• Ali Iranli and Massoud Pedram, Cycle-based Decomposition of Markov Chains with Applications to Low Power Synthesis and Sequence Compaction for Finite State Machines (2879)

• Fei Su and Krishnendu Chakrabarty, Defect Tolerance Based on Graceful Degradation and Dynamic Reconfiguration for Digital Microfluidics (2950)

• Aditya Bansal, Bipul C Paul, Kaushik Roy, An Analytical Fringe Capacitance Model for Interconnects using Conformal Mapping (2854)

• Lei Cheng and Martin D.F. Wong, Floorplan Design for Multi-Million Gate FPGAs (2846)

• Zhao Li and C.-J. Richard Shi, A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits with Strong Parasitic Couplings (2816)

• Debjit Sinha and Hai Zhou, Statistical Timing Analysis with Coupling (2927)

• S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang and T. Kam, Reducing Structural Bias in Technology Mapping (2807)

• Kaviraj Chopra and Sarma Vrudhula, Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States (2843)

• Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi and Xu Xu, Wafer Topography-Aware Optical Proximity Correction (2830)

• K. Patel, L. Benini, E. Macii and M. Poncino, Reducing Conflict Misses by Application-Specific Re-Configurable Indexing (2804)

• Xiaochun Duan and Kartikeya Mayaram, Frequency-Domain Simulation of Ring Oscillators with a Multiple-probe Method (2922)

• Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak and Jason Cong, Protecting Combinational Logic Synthesis Solutions (2774)

• C. Chantrapornchai, W. Surakumpolthorn and E. H-M. Sha, Design Exploration with Imprecise Latency and Register Constraints (2940)

• Mehrdad Reshadi, Bita Gorjiara and Nikil Dutt, Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators (3007)

• Pu Liu, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan and Jun Yang, Fast Thermal Simulation for Run-Time Temperature Tracking and Management (2915)

• Ravishankar Rao and Sarma Vrudhula, Energy optimal speed control of a generic device (2921)

• Xiaochun Duan and Kartikeya Mayaram, Robust Simulation of High-Q Oscillators Using a Homotopy Based Harmonic Balance Method (2877)

• Wei-Shen Wang and Michael Orshansky, Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation (2899)

• Muhammet Mustafa Ozdal and Martin D. F. Wong, A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards (3055)

• M.M. Vaseekar Kumar, S. Tragoudas, S. Chakravarty and R. Jayabharathi, Exact Delay Fault Coverage in Sequential Logic under any Delay Fault Model (2887)

• Peng Li, Statistical Sampling Based Parametric Analysis of Power Grids (2925)

• Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury and Kaushik Roy, A Novel Delay Fault Testing Methodology Using Low-Overhead Built-in Delay Sensor (2787)

• Jie-Hong R. Jiang and Robert K. Brayton, Retiming and Resynthesis: A Complexity Perspective (2926)

• Le Cai, Nathaniel Pettis, and Yung-Hsiang Lu, Joint Power Management of Memory and Disk Under Performance Constraints (3062)

• Natasa Miskpov-Zivanov and Diana Marculescu, Circuit Reliability Analysis Using Symbolic Techniques (3014)

• Yuantao Peng and Xun Liu, An Efficient Low-power Repeater Insertion Scheme (2951)

Short Papers:

• Ruiming Chen and Hai Zhou, An Efficient Data Structure for Maxplus Merge in Dynamic Programming (2837)

• Xiren Wang, Wenjian Yu and Zeyi Wang, Efficient Direct Boundary Element Method for Resistance Extraction of Substrate with Arbitrary Doping Profile (2918)

• Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor and Sultan Al-Harbi, Influence of Bit Line Coupling and Twisting on the Faulty Behavior of DRAMs (2803)

• Mario R. Casu and Luca Macchiarulo, Floorplanning with Wire Pipelining in Adaptive Communication Channels (2882)

• Azadeh Davoodi and Ankur Srivastava, Probabilistic Evaluation of Solutions in Variability-Driven Optimization (2868)

• Stelios N. Neophytou, Maria K. Michael and Spyros Tragoudas, Functions for Quality Transition Fault Tests and their Applications in Test Set Enhancement (2871)

• Mongkol Ekpanyapong, Michael Healy and Sung Kyu Lim, Profile-Driven Instruction Mapping for Dataflow Architectures (2968)

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