IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Year Cited Authors Cited Work Volume
       
1990 Pillage LT, Rohrer RA Asymptotic Wave-Form Evaluation For Timing Analysis 9 (4): 352-366
1990 Wachutka GK Rigorous Thermodynamic Treatment Of Heat-Generation And Conduction In Semiconductor-Device Modeling 9 (11): 1141-1149
1990 Serra M, Slater T, Muzio JC, Miller DM The Analysis Of One-Dimensional Linear Cellular Automata And Their Aliasing Properties 9 (7): 767-778
1990 Villa T, Sangiovannivincentelli A Nova - State Assignment Of Finite State Machines For Optimal 2-Level Logic Implementation 9 (9): 905-924
1990 Shahookar K, Mazumder P A Genetic Approach To Standard Cell Placement Using Meta-Genetic Parameter Optimization 9 (5): 500-511
1990 Najm FN, Burch R, Yang P, Hajj IN Probabilistic Simulation For Reliability-Analysis Of CMOS VLSI Circuits 9 (4): 439-450
1990 Dekker R, Beenker F, Thijssen L A Realistic Fault Model And Test Algorithms For Static Random-Access Memories 9 (6): 567-572
1990 Ho JM, Vijayan G, Wong CK New Algorithms For The Rectilinear Steiner Tree Problem 9 (2): 185-193
1990 Chiang C, Sarrafzadeh M, Wong CK Global Routing Based On Steiner MIN-MAX Trees 9 (12): 1318-1325
1990 Yamamura K, Horiuchi K A Globally And Quadratically Convergent Algorithm For Solving Nonlinear Resistive-Networks 9 (5): 487-499
1990 Devadas S, Ma HKT, Newton AR, Sangiovannivincentelli A Irredundant Sequential-Machines Via Optimal Logic Synthesis 9 (1): 8-18
 
1991 Nabors K, White J Fastcap - A Multipole Accelerated 3-D Capacitance Extraction Program 10 (11): 1447-1459
1991 Hwang CT, Lee JH, Hsu YC A Formal Approach To The Scheduling Problem In High-Level Synthesis 10 (4): 464-475
1991 Fatemi E, Jerome J, Osher S Solution Of The Hydrodynamic Device Model Using High-Order Nonoscillatory Shock Capturing Algorithms 10 (2): 232-244
1991 Cohoone JP, Hegde SU, Martin WN, Richards DS Distributed Genetic Algorithms For The Floorplan Design Problem 10 (4): 483-492
1991 Kleinhans JM, Sigl G, Johannes FM, Antreich KJ Gordian - VLSI Placement By Quadratic-Programming And Slicing Optimization 10 (3): 356-365
1991 Camposano R Path-Based Scheduling For Synthesis 10 (1): 85-93
1991 Cheng CK, Wei YCA An Improved 2-Way Partitioning Algorithm With Stable Performance 10 (12): 1502-1511
1991 Park HJ, Ko PK, Hu CM A Charge Sheet Capacitance Model Of Short Channel MOSFETS For SPICE 10 (3): 376-389
1991 Boothroyd AR, Tarasewicz SW, Slaby C Misnan - A Physically Based Continuous MOSFET Model For CAD Applications 10 (12): 1512-1529
1991 Fuchs K, Schulz MH Dynamite - An Efficient Automatic Test Pattern Generation System For Path Delay Faults 10 (10): 1323-1335
1991 Saab YG, Rao VB Combinatorial Optimization By Stochastic-Evolution 10 (4): 525-535
       
1992 Tang TK, Nakhla MS Analysis Of High-Speed VLSI Interconnects Using The Asymptotic Wave-Form Evaluation Technique 11 (3): 341-352
1992 Larrabee T Test Pattern Generation Using Boolean Satisfiability 11 (1): 4-15
1992 Hagen L, Kahng AB New Spectral Methods For Ratio Cut Partitioning And Clustering 11 (9): 1074-1085
1992 Niermann TM, Cheng WT, Patel JH Proofs - A Fast, Memory-Efficient Sequential-Circuit Fault Simulator 11 (2): 198-207
1992 Cong JS, Kahng AB, Robins G, Sarrafzadeh M, Wong CK Provably Good Performance-Driven Global Routing 11 (6): 739-752
1992 Kahng AB, Robins G A New Class Of Iterative Steiner Tree Heuristics With Good Performance 11 (7): 893-902
1992 Brown S, Rose J, Vranesic ZG A Detailed Router For Field-Programmable Gate Arrays 11 (5): 620-628
1992 Bernardo MC, Buck R, Liu LS, Nazaret WA, Sacks J, Welch WJ Integrated-Circuit Design Optimization Using A Sequential Strategy 11 (3): 361-372
1992 Devadas S, Keutzer K, White J Estimation Of Power Dissipation In CMOS Combinational-Circuits Using Boolean Function Manipulation 11 (3): 373-383
1992 Falkowski BJ, Schafer I, Perkowski MA Effective Computer Methods For The Calculation Of Rademacher-Walsh Spectrum For Completely And Incompletely Specified Boolean Functions 11 (10): 1207-1226
 
1993 Najm FN Transition Density - A New Measure Of Activity In Digital Circuits 12 (2): 310-323
1993 Sapatnekar SS, Rao VB, Vaidya PM, Kang SM An Exact Solution To The Transistor Sizing Problem For CMOS Circuits Using Convex-Optimization 12 (11): 1621-1634
1993 Sasao T Exmin2 - A Simplification Algorithm For Exclusive-OR-Sum-Of Products Expressions For Multiple-Valued-Input 2-Valued-Output Functions 12 (5): 621-632
1993 Chakradhar ST, Agrawal VD, Rothweiler SG A Transitive Closure Algorithm For Test-Generation 12 (7): 1015-1028
1993 Cho H, Hachtel GD, Somenzi F Redundancy Identification Removal And Test-Generation For Sequential-Circuits Using Implicit State Enumeration 12 (7): 935-945
1993 Chen HC, Du DH Path Sensitization In Critical Path Problem 12 (2): 196-207
1993 Melville RC, Trajkovic L, Fang SC, Watson LT Artificial Parameter Homotopy Methods For The DC Operating Point Problem 12 (6): 861-877
 
1994 Burch JR, Clarke EM, Long DE, McMillan KL, Dill DL Symbolic Model Checking For Sequential-Circuit Verification 13 (4): 401-424
1994 Cong J, Ding YH Flowmap - An Optimal Technology Mapping Algorithm For Delay Optimization In Lookup-Table Based FPGA Designs 13 (1): 1-12
1994 Qian J, Pullela S, Pillage L Modeling The Effective Capacitance For The RC Interconnect Of CMOS Gates 13 (12): 1526-1535
1994 Ratzlaff CL, Pillage LT RICE - Rapid Interconnect Circuit Evaluation Using AWE 13 (6): 763-776
1994 Choi WS, Ahn JG, Park YJ, Min HS, Hwang CG A Time-Dependent Hydrodynamic Device Simulator SNU-2D With New Discretization Scheme And Algorithm 13 (7): 899-908
1994 Nabavilishi A, Rumin NC Inverter Models Of CMOS Gates For Supply Current And Delay Evaluation 13 (10): 1271-1279
1994 Kunz W, Pradhan DK Recursive Learning - A New Implication Technique For Efficient Solutions To CAD Problems - Test, Verification, And Optimization 13 (9): 1143-1158
 
1995 Feldmann P, Freund RW Efficient Linear Circuit Analysis By Pade-Approximation Via The Lanczos Process 14 (5): 639-649
1995 Chiprout E, Nakhla MS Analysis Of Interconnect Networks Using Complex Frequency-Hopping (CFH) 14 (2): 186-200
1995 Chandrakasan AP, Potkonjak M, Mehra R, Rabaey J, Brodersen RW Optimizing Power Using Transformations 14 (1): 12-31
1995 Cong JJS, Leung KS Optimal Wiresizing Under Elmore Delay Model 14 (3): 321-336
 
1996 Murata H, Fujiyoshi K, Nakatake S, Kajitani Y VLSI module placement based on rectangle-packing by the sequence-pair 15 (12): 1518-1524
1996 Potkonjak M, Srivastava MB, Chandrakasan AP Multiple constant multiplications: Efficient and versatile framework and algorithms for exploring common subexpression elimination 15 (2): 151-165
1996 Ochotta ES, Rutenbar RA, Carley LR Synthesis of high-performance analog circuits in ASTRX/OBLX 15 (3): 273-294
1996 Benini L, DeMicheli G Automatic synthesis of low-power gated-clock finite-state machines 15 (6): 630-643
1996 Marculescu D, Marculescu R, Pedram M Information theoretic measures for power analysis 15 (6): 599-610
1996 MiuraMattausch M, Feldmann U, Rahm A, Bollu M Unified complete MOSFET model for analysis of digital and analog circuits 15 (1): 1-7
1996 Arora ND, Raol KV, Schumann R, Richardson LM Modeling and extraction of interconnect capacitances for multilayer VLSI circuits 15 (1): 58-67
1996 Nemani M, Najm FN Towards a high-level power estimation capability 15 (6): 588-598
 
1997 Phillips JR, White JK A precorrected-FFT method for electrostatic analysis of complicated 3-D structures 16 (10): 1059-1072
1997 Wasshuber C, Kosina H, Selberherr S SIMON - A simulator for single-electron tunnel devices and circuits 16 (9): 937-944
1997 Vittal A, MarekSadowska M Crosstalk reduction for VLSI 16 (3): 290-298
 
1998 Odabasioglu A, Celik M, Pileggi LT PRIMA: Passive reduced-order interconnect macromodeling algorithm 17 (8): 645-654
1998 Macii E, Pedram M, Somenzi F High-level power modeling, estimation, and optimization 17 (11): 1061-1079
1998 Lee EA, Sangiovanni-Vincentelli A A framework for comparing models of computation 17 (12): 1217-1229
1998 Dabholkar V, Chakravarty S, Pomeranz I, Reddy S Techniques for minimizing power dissipation in scan and combinational circuits during test application 17 (12): 1325-1333
 
2000 Keutzer K, Malik S, Newton AR, Rabaey JM, Sangiovanni-Vincentelli A System-level design: Orthogonalization of concerns and platform-based design 19 (12): 1523-1543