| 1990 |
Pillage, L.T.; Rohrer, R.A. |
Asymptotic waveform evaluation for timing analysis |
9 |
4 |
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| 1994 |
Gowda, S.M.; Sheu, B.J.; |
BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits |
13 |
9 |
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| 2000 |
Wakabayashi, K.; Okamoto, T. |
C-based SoC design flow and EDA tools: an ASIC and system vendor |
19 |
12 |
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| 2003 |
Kirovski, D.; Potkonjak, M.; |
Local watermarks: methodology and application to behavioral synthesis |
22 |
9 |
| 2003 |
Chandra, A.; Chakrabarty, K.; |
A unified approach to reduce SOC test data volume, scan power and testing time |
22 |
3 |
| 2003 |
Binkley, D.M.; Hopper, C.E.; Tucker, S.D.; Moss, B.C.; Rochelle, J.M.; Foty, D.P. |
A CAD methodology for optimizing transistor current and sizing in analog CMOS design |
22 |
2 |
| 2003 |
Dick, R.P.; Lakshminarayana, G.; Raghunathan, A.; Jha, N.K. |
Analysis of power dissipation in embedded systems using real-time operating systems |
22 |
5 |
| 2003 |
Doboli, A.; Vemuri, R. |
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS |
22 |
11 |
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| 2004 |
Bhattacharjee, S.; Pradhan, D.K.; |
LPRAM: a novel low-power high-performance RAM design with testability and scalability |
23 |
5 |
| 2004 |
Nahvi, M.; Ivanov, A. |
Indirect test architecture for SoC testing |
23 |
7 |
| 2004 |
Kyeong Keol Ryu; Mooney, V.J., III |
Automated bus generation for multiprocessor SoC design |
23 |
11 |
| 2004 |
Raychowdhury, A.; Mukhopadhyay, S.; Roy, K. |
A circuit-compatible model of ballistic carbon nanotube field-effect transistors |
23 |
10 |
| 2004 |
Lahiri, K.; Raghunathan, A.; Dey, S. |
Efficient power profiling for battery-driven embedded system design |
23 |
6 |
| 2004 |
Lahiri, K.; Raghunathan, A.; Dey, S. |
Design space exploration for optimizing on-chip communication architectures |
23 |
6 |
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| 2005 |
Rui Zhang; Gupta, P.; Lin Zhong; Jha, N.K. |
Threshold network synthesis and optimization and its application to nanotechnologies |
24 |
1 |
| 2005 |
Bourenkov, V.; McCarthy, K.G.; Mathewson, A. |
MOS table models for circuit simulation |
24 |
3 |
| 2005 |
Tan, S.X.-D. |
A general hierarchical circuit modeling and simulation algorithm |
24 |
3 |
| 2005 |
Heydari, P.; Pedram, M. |
Capacitive coupling noise in high-speed VLSI circuits |
24 |
3 |
| 2005 |
Peng Li; Pileggi, L.T. |
Compact reduced-order modeling of weakly nonlinear analog and RF circuits |
24 |
2 |
| 2005 |
La Rosa, A.; Lavagno, L.; Passerone, C. |
Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform |
24 |
1 |
| 2005 |
Lin Zhong; Jha, N.K.; |
Interconnect-aware low-power high-level synthesis |
24 |
3 |
| 2005 |
Guoqing Chen; Friedman, E.G. |
An RLC interconnect model based on fourier analysis |
24 |
2 |
| 2005 |
Pecheux, F.; Lallement, C.; Vachoux, A. |
VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems |
24 |
2 |
| 2005 |
Badaroglu, M.; Wambacq, P.; Van der Plas, G.; Donnay, S.; Gielen, G.G.E.; De Man, H.J.; |
Digital ground bounce reduction by supply current shaping and clock frequency Modulation |
24 |
1 |
| 2005 |
Mukhopadhyay, S.; Raychowdhury, A.; Roy, K. |
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile |
24 |
3 |