| Top 25 Articles for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems PDFs Downloaded from January - December 2008 |
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| Source of Statistics: IEEE Xplore weblogs. Note: These are not COUNTER-compliant usage statistics, which means they have not been scrubbed for automatic download tools. See worksheet for ranking of periodical titles based on overall 2008 usage. | |||
| Article Title | Volume | Issue | 2008 Jan - Dec Use By Article |
| Statistical Timing Analysis: From Basic Principles to State of the Art | 27 | 4 | 948 |
| Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks | 26 | 1 | 596 |
| DC-DC Converter-Aware Power Management for Low-Power Embedded Systems | 26 | 8 | 566 |
| CMP Fill Synthesis: A Survey of Recent Studies | 27 | 1 | 465 |
| VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems | 24 | 2 | 429 |
| Asymptotic Probability Extraction for Nonnormal Performance Distributions | 26 | 1 | 401 |
| Systematic and Automated Multiprocessor System Design, Programming, and Implementation | 27 | 3 | 398 |
| A Survey of Automated Techniques for Formal Software Verification | 27 | 7 | 384 |
| Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations | 27 | 3 | 382 |
| System-Level Dynamic Thermal Management for High-Performance Microprocessors | 27 | 1 | 367 |
| Power modeling and characteristics of field programmable gate arrays | 24 | 11 | 354 |
| Asymptotic waveform evaluation for timing analysis | 9 | 4 | 350 |
| Measuring the Gap Between FPGAs and ASICs | 26 | 2 | 341 |
| Variability-Aware Bulk-MOS Device Design | 27 | 2 | 340 |
| Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias | 27 | 1 | 337 |
| Analysis of power dissipation in embedded systems using real-time operating systems | 22 | 5 | 333 |
| Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog | 27 | 2 | 330 |
| Optimizing Thermal Sensor Allocation for Microprocessors | 27 | 3 | 320 |
| Quantum Circuit Simplification and Level Compaction | 27 | 3 | 317 |
| Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS | 24 | 12 | 317 |
| Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration | 27 | 3 | 316 |
| A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm | 27 | 3 | 313 |
| Testing Network-on-Chip Communication Fabrics | 26 | 12 | 308 |
| Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis | 26 | 10 | 307 |
| A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters | 27 | 2 | 301 |